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參數(shù)資料
| 型號： | M68HC05M68H |
| 廠商： | Motorola, Inc. |
| 英文描述： | HCMOS Microcontroller Unit |
| 中文描述： | HCMOS微控制器 |
| 文件頁數(shù)： | 40/130頁 |
| 文件大?。?/td> | 1541K |
| 代理商： | M68HC05M68H |
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Operating Modes
Advance Information
MC68HC705P6A
—
Rev. 2.0
40
Operating Modes
MOTOROLA
timer (a feature of the stop mode), which has been free-running (a
feature of the wait mode).
3.5.2 WAIT Instruction
The WAIT instruction places the MCU in a low-power mode which
consumes more power than stop mode. In wait mode, the internal clock
is halted, suspending all processor and internal bus activity. Internal
timer clocks remain active, permitting interrupts to be generated from the
16-bit timer and reset to be generated from the COP watchdog timer.
Execution of the WAIT instruction automatically clears the I bit in the
condition code register, enabling the IRQ external interrupt. All other
registers, memory, and input/output lines remain in their previous state.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit
wait mode and resume normal operation. The 16-bit timer may be used
to generate a periodic exit from wait mode. Wait mode may also be
exited when an IRQ external interrupt or RESET occurs.
3.6 COP Watchdog Timer Considerations
The COP watchdog timer is active in user mode of operation when the
COP bit in the MOR is set. Executing the STOP instruction when the
SWAIT bit in the MOR is clear will cause the COP to be disabled.
Therefore, it is recommended that the STOP instruction be modified to
produce halt mode (set bit SWAIT in the MOR) if the COP watchdog
timer is required to function at all times.
Furthermore, it is recommended that the COP watchdog timer be
disabled for applications that will use the wait mode for time periods that
will exceed the COP timeout period.
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