參數(shù)資料
型號(hào): M54HC367C1R
廠商: 意法半導(dǎo)體
英文描述: CONNECTOR ACCESSORY
中文描述: 連接器附件
文件頁數(shù): 1/11頁
文件大?。?/td> 249K
代理商: M54HC367C1R
M54/M74HC367
M54/M74HC368
October 1992
HC367NONINVERTING,HC368 INVERTING
HEX BUS BUFFER (3-STATE)
B1R
(Plastic Package)
ORDER CODES :
M54HCXXXF1R
M74HCXXXB1R
M74HCXXXM1R
M74HCXXXC1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
HC368
HC367
DESCRIPTION
.
HIGH SPEED
t
PD
= 11 ns(TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 6 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS367/368
The M54/74HC367 and the M54/74HC368 are high
speedCMOS HEXBUS BUFFER (3-STATE) fabri-
catedin silicon gate C
2
MOS technology. Theyhave
the same high speed performance of LSTTL com-
bined with true CMOS low power consumption.
These devices contain six buffers, four buffers are
controlled byan enable input (G1)andtheother two
buffers are controlled by the other enable input
(G2); theoutputs of each buffer group are enabled
when G1 and/or G2 inputs are held low, and
when held high these outputs are disabled to be
high-impedance.
Theseoutputs arecapableofdriving upto15LSTTL
loads. The designer has a choice of non-inverting
outputs (HC367) and inverting outputs (HC368).
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
1/11
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