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參數(shù)資料
| 型號(hào)： | M48Z59 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64Kb (8K x 8) ZEROPOWER SRAM(64K零功耗SRAM) |
| 中文描述： | 64Kb的（8K的× 8）ZEROPOWER的SRAM（64K的零功耗的SRAM） |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 137K |
| 代理商： | M48Z59 |
M48Z59
M48Z59Y
64Kb (8K x 8) ZEROPOWER
SRAM
January 1998
1/14
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
– M48Z59: 4.50V
≤
V
PFD
≤
4.75V
– M48Z59Y: 4.20V
≤
V
PFD
≤
4.50V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT
TOP
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 8K x 8 SRAMs
DESCRIPTION
The M48Z59/59Y ZEROPOWER
RAM is an 8K x
8 non-volatile static RAM that integrates power-fail
deselect circuitry and battery control logic on a
single die. The monolithic chip is available in two
special packages to provide a highly integrated
battery backed-up memory solution.
AI01179B
13
A0-A12
W
DQ0-DQ7
VCC
M48Z59
M48Z59Y
G
E2
VSS
8
E1
RST
Figure 1. Logic Diagram
A0-A12
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
RST
Power Fail Reset Ouput (Open Drain)
E1
Chip Enable 1
E2
Chip Enable 2
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
28
1
PCDIP28 (PC)
Battery CAPHAT
SNAPHAT (SH)
Battery
28
1
SOH28 (MH)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M48Z59Y | 64Kb (8K x 8) ZEROPOWER SRAM(64K零功耗SRAM) |
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| M500420R2PK | 9x16 mm FR-4, 5.0 Volt, CMOS/TTL/PECL/LVDS, HPVCXO |
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參數(shù)描述 |
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