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參數(shù)資料
| 型號： | M48T35Y-70PC6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP28 |
| 封裝： | 0.600 INCH, CAPHAT, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 26/26頁 |
| 文件大?。?/td> | 349K |
| 代理商： | M48T35Y-70PC6 |
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M48T35, M48T35Y
OPERATION MODES
As Figure 6, page 5 shows, the static memory ar-
ray and the quartz controlled clock oscillator of the
M48T35/Y are integrated on one silicon chip. The
two circuits are interconnected at the upper eight
memory locations to provide user accessible
BYTEWIDE clock information in the bytes with ad-
dresses 7FF8h-7FFFh.
The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD for-
mat. Corrections for 28, 29 (leap year - valid until
2100), 30, and 31 day months are made automat-
ically. Byte 7FF8h is the clock control register. This
byte controls user access to the clock information
and also stores the clock calibration setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT READ/WRITE memory
cells. The M48T35/Y includes a clock control cir-
cuit which updates the clock bytes with current in-
formation once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T35/Y also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
tion. When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of
data security in the midst of unpredictable system
operation brought on by low VCC. As VCC falls be-
low the Battery Back-up Switchover Voltage
(VSO), the control circuitry connects the battery
which maintains data and clock operation until val-
id power returns.
Table 6. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 10, page 14 for details.
Mode
VCC
E
G
W
DQ0-DQ7
Power
Deselect
4.75 to 5.5V
or
4.5 to 5.5V
VIH
X
High Z
Standby
WRITE
VIL
X
VIL
DIN
Active
READ
VIL
VIH
DOUT
Active
READ
VIL
VIH
High Z
Active
Deselect
VSO to VPFD (min)
(1)
X
High Z
CMOS Standby
Deselect
≤ VSO(1)
X
High Z
Battery Back-up Mode
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| M48T35Y-70PC6E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 256 Kbit (32 Kb x 8) TIMEKEEPER SRAM |
| M48T35Y-70PC6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 256 Kbit (32 Kb x 8) TIMEKEEPER SRAM |
| M48T35Y-70PC6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T35Y-70PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 256 Kbit (32 Kb x 8) TIMEKEEPER SRAM |
| M48T35Y-70PM1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 256 Kbit (32 Kb x 8) TIMEKEEPER SRAM |
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