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  1. 參數(shù)資料
    型號(hào): M38514E6SS
    元件分類: 微控制器/微處理器
    英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, CDIP42
    封裝: 0.600 INCH, METAL SEALED, DIP-42
    文件頁(yè)數(shù): 83/91頁(yè)
    文件大?。?/td> 1295K
    代理商: M38514E6SS
    84
    SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
    MITSUBISHI MICROCOMPUTERS
    3851 Group
    (Built-in 24 KB or more ROM)
    Timing requirements
    Table 32 Timing requirements (1)
    (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
    Reset input “L” pulse width
    External clock input cycle time
    External clock input “H” pulse width
    External clock input “L” pulse width
    CNTR0, CNTR1 input cycle time
    CNTR0, CNTR1 input “H” pulse width
    CNTR0, CNTR1 input “L” pulse width
    INT0 to INT3 input “H” pulse width
    INT0 to INT3 input “L” pulse width
    Serial I/O1 clock input cycle time (Note)
    Limits
    XIN cycle
    ns
    Parameter
    Min.
    20
    125
    50
    200
    80
    800
    370
    220
    100
    1000
    400
    200
    Typ.
    Max.
    Symbol
    Unit
    Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
    Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
    Serial I/O1 clock input “H” pulse width (Note)
    Serial I/O1 clock input “L” pulse width (Note)
    Serial I/O1 input setup time
    Serial I/O1 input hold time
    Serial I/O2 clock input cycle time
    Serial I/O2 clock input “H” pulse width
    Serial I/O2 clock input “L” pulse width
    Serial I/O2 clock input setup time
    Serial I/O2 clock input hold time
    Table 33 Timing requirements (2)
    (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
    tW(RESET)
    tC(XIN)
    tWH(XIN)
    tWL(XIN)
    tC(CNTR)
    tWH(CNTR)
    tWL(CNTR)
    tWH(INT)
    tWL(INT)
    tC(SCLK1)
    tWH(SCLK1)
    tWL(SCLK1)
    tsu(RxD-SCLK1)
    th(SCLK1-RxD)
    tC(SCLK2)
    tWH(SCLK2)
    tWL(SCLK2)
    tsu(SIN2-SCLK2)
    th(SCLK2-SIN2)
    Reset input “L” pulse width
    External clock input cycle time
    External clock input “H” pulse width
    External clock input “L” pulse width
    CNTR0, CNTR1 input cycle time
    CNTR0, CNTR1 input “H” pulse width
    CNTR0, CNTR1 input “L” pulse width
    INT0 to INT3 input “H” pulse width
    INT0 to INT3 input “L” pulse width
    Serial I/O1 clock input cycle time (Note)
    Serial I/O1 clock input “H” pulse width (Note)
    Serial I/O1 clock input “L” pulse width (Note)
    Serial I/O1 input setup time
    Serial I/O1 input hold time
    Serial I/O2 clock input cycle time
    Serial I/O2 clock input “H” pulse width
    Serial I/O2 clock input “L” pulse width
    Serial I/O2 clock input setup time
    Serial I/O2 clock input hold time
    tW(RESET)
    tC(XIN)
    tWH(XIN)
    tWL(XIN)
    tC(CNTR)
    tWH(CNTR)
    tWL(CNTR)
    tWH(INT)
    tWL(INT)
    tC(SCLK1)
    tWH(SCLK1)
    tWL(SCLK1)
    tsu(RxD-SCLK1)
    th(SCLK1-RxD)
    tC(SCLK2)
    tWH(SCLK2)
    tWL(SCLK2)
    tsu(SIN2-SCLK2)
    th(SCLK2-SIN2)
    Limits
    XIN cycle
    ns
    Parameter
    Min.
    20
    250
    100
    500
    230
    2000
    950
    400
    200
    2000
    950
    400
    300
    Typ.
    Max.
    Symbol
    Unit
    Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
    Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART).
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