• 參數(shù)資料
    型號(hào)： CD-700-LAF-GFB-34.368
    英文描述： Phase-Locked Loop
    中文描述： 鎖相環(huán)
    文件頁(yè)數(shù)： 5/14頁(yè)
    文件大?。?/td> 141K
    代理商： CD-700-LAF-GFB-34.368
    CD-700, VCXO Based PLL
    Vectron International
    166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 http://www.vectron.com
    1
    9
    5
    6
    8
    13
    14
    16
    CLAFGAB
    FREQUENCY
    VI YWW
    23 4
    7
    10
    11
    12
    15
    Figure 14. Outline Diagram
    Table 5. Pin Function
    Pin
    Symbol
    Function
    1
    OPOUT
    Op-Amp Output
    2
    OPN
    Op-Amp Negative Input
    3
    PHO
    Phase detector output
    4
    LOSIN
    INPUT (Used with LOS)
    Logic 0, VCXO control voltage is enabled.
    Logic 1, VCXO control voltage (pin 16) is disabled and OUT1 and OUT2 are within +/-75 ppm
    of center frequency
    Has Internal pull-down resistor
    5
    DATAIN
    Phase detector Input signal (TTL switching thresholds)
    6
    CLKIN
    Phase detector Clock signal (TTL switching thresholds)
    7
    GND
    Cover and Electrical Ground
    8
    LOS
    OUTPUT (Used with LOSIN)
    Logic 1 if there are no transitions detected at DATAIN after 256 clock cycles at CLKIN. As soon
    as a transition occurs at DATAIN, LOS is set to a logic low.
    Logic 0 = Input frequency detected
    9
    RCLK
    Recovered Clock
    10
    RDATA
    Recovered Data
    11
    Output 2
    Divided-down VCXO Output, or No Output
    12
    HIZ
    INPUT
    Logic 0, OUT1, OUT2, RCLK, RDATA are set to a high impedance state.
    Logic 1, OUT1, OUT2, RCLK, RDATA are active.
    Has Internal pull-up resistor
    13
    Output 1
    VCXO Output
    14
    VDD
    Power Supply Voltage (3.3 V
    ±10% or 5.0 V ±10%)
    15
    OPP
    Op-Amp Positive Input
    16
    VC
    VCXO Control Voltage
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