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參數資料
| 型號： | LTC692 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Microprocessor Supervisory Circuits(μP監(jiān)控電路) |
| 中文描述： | 微處理器監(jiān)控電路（微處理器監(jiān)控電路） |
| 文件頁數： | 10/16頁 |
| 文件大?。?/td> | 261K |
| 代理商： | LTC692 |
10
LTC692/LTC693
V
CC
V1
CE IN
V
OUT
= V
BATT
CE OUT
V
OUT
= V
BATT
V2
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
LTC692/3 F05
Memory Protection
The LTC693 includes memory protection circuitry which
ensures the integrity of the data in memory by preventing
write operations when V
CC
is at an invalid level. Two
additional pins, CE IN and CE OUT, control the Chip Enable
or Write inputs of CMOS RAM. When V
CC
is 5V, CE OUT
follows CE IN with a typical propagation delay of 20ns.
When V
CC
falls below the reset voltage threshold or V
BATT
,
CE OUT is forced high, independent of CE IN. CE OUT is an
U
S
A
O
PPLICATI
U
U
If battery connections are made through long wires, a 10
to 100
series resistor and a 0.1
μ
F capacitor are recom-
mended to prevent any overshoot beyond V
CC
due to the
lead inductance (Figure 4).
alternative signal to drive the CE, CS, or Write input of
battery backed up CMOS RAM. CE OUT can also be used
to drive the Store or Write input of an EEPROM, EAROM or
NOVRAM to achieve similar protection. Figure 5 shows the
timing diagram of CE IN and CE OUT.
CE IN can be derived from the microprocessor's address
decoder output. Figure 6 shows a typical nonvolatile
CMOS RAM application.
Memory protection can also be achieved with the LTC692
by using RESET as shown in Figure 7.
SIGNAL
V
CC
V
OUT
V
BATT
BATT ON
PFI
PFO
RESET
RESET
LOW LINE Logic low
WDI
WDO
CE IN
CE OUT
OSC IN
OSC SEL
STATUS
C2 monitors V
CC
for active switchover.
V
OUT
is connected to V
BATT
through an internal PMOS switch.
The supply current is 1
μ
A maximum.
Logic high. The open-circuit output voltage is equal to V
OUT
.
Power Failure Input is ignored.
Logic low
Logic low
Logic high. The open-circuit output voltage is equal to V
OUT
.
Watchdog Input is ignored.
Logic high. The open-circuit output voltage is equal to V
OUT
.
Chip Enable Input is ignored.
Logic high. The open-circuit output voltage is equal to V
OUT
.
OSC IN is ignored.
OSC SEL is ignored.
Table 1. Input and Output Status in Battery Backup Mode
3.9M
0.1μF
V
BATT
LTC692
LTC693
GND
LTC692/3 F04
10
Figure 4. 10
/0.1
μ
F combination eliminates inductive
overshoot and prevents spurious resets during battery
replacement.
Table 1 shows the state of each pin during battery backup.
When the battery switchover section is not used, connect
V
BATT
to GND and V
OUT
to V
CC
.
Figure 5. Timing Diagram for CE IN and CE OUT
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LTC692_09 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Microprocessor Supervisory Circuits |
| LTC692C | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Microprocessor Supervisory Circuits |
| LTC692CN8 | 功能描述:IC MPU SUPERVISORY CIRCUIT 8-DIP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:1 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數目:1 輸出:開路漏極或開路集電極 復位:高有效 復位超時:- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線 供應商設備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱:NCP301HSN18T1GOSCT |
| LTC692CN8#PBF | 功能描述:IC MPU SUPERVISORY CIRCUIT 8-DIP RoHS:是 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:1 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數目:1 輸出:開路漏極或開路集電極 復位:高有效 復位超時:- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線 供應商設備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱:NCP301HSN18T1GOSCT |
| LTC692CN8-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Microprocessor Supervisory Circuits |
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