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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD7357BRUZ-500RL7 |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 18/21闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC ADC DUAL14BIT 4.2MSPS 16TSSOP |
| 瑷�(sh猫)瑷堣硣婧愶細 | DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7357 (CN0061) |
| 妯欐簴鍖呰锛� | 500 |
| 浣嶆暩(sh霉)锛� | 14 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 4.2M |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 2 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 59mW |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-TSSOP锛�0.173"锛�4.40mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-TSSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 2 鍊嬪樊鍒�锛岄洐妤� |
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AD7357
Rev. B | Page 5 of 20
TIMING SPECIFICATIONS
VDD = 2.5 V 卤 10%, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, TA = TMAX to TMIN1, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
fSCLK
500
kHz min
80
MHz max
tCONVERT
t2 + 15.5 脳 tSCLK
ns min
tSCLK = 1/fSCLK
tQUIET
5
ns min
Minimum time between end of serial read and next falling edge of CS
t2
5
ns min
CS to SCLK setup time
6
ns max
Delay from CS until SDATAA and SDATAB are three-state disabled
Data access time after SCLK falling edge
12.5
ns max
1.8 V 鈮� VDRIVE < 2.25 V
11
ns max
2.25 V 鈮� VDRIVE < 2.75 V
9.5
ns max
2.75 V 鈮� VDRIVE < 3.3 V
9
ns max
3.3 V 鈮� VDRIVE 鈮� 3.6 V
t5
5
ns min
SCLK low pulse width
t6
5
ns min
SCLK high pulse width
t72
SCLK to data valid hold time
3.5
ns min
1.8 V 鈮� VDRIVE < 2.75 V
3
ns min
2.75 V 鈮� VDRIVE 鈮� 3.6 V
t8
9.5
ns max
CS rising edge to SDATA , SDATAB, high impedance
A
t9
5
ns min
CS rising edge to falling edge pulse width
t102
4.5
ns min
SCLK falling edge to SDATAA, SDATAB, high impedance
9.5
ns max
SCLK falling edge to SDATAA, SDATAB, high impedance
Latency
1 conversion latency
1 Temperature ranges are as follows: AD7357Y: 40掳C to +125掳C, AD7357B: 40掳C to +85掳C, AD7357WY: 40掳C to +125掳C.
2 Specified with a load capacitance of 10 pF on SDATAA and SDATAB.
3 The time required for the output to cross 0.4 V or 2.4 V.
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AD7357BRUZ-RL | 鍔熻兘鎻忚堪:IC ADC 14BITDUAL 4.MSPS 16TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯欐簴鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:300k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:75mW 闆诲闆绘簮:鍠浕婧� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:24-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:24-SOIC 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:1 鍊嬪柈绔�锛屽柈妤�锛�1 鍊嬪柈绔紝闆欐サ |
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| AD7357WYRUZ-RL | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC 14-Bit Dual Diff Simult 5 MSPS RoHS:鍚� 鍒堕€犲晢:Analog Devices 閫氶亾鏁�(sh霉)閲�: 绲�(ji茅)妲�(g貌u): 杞�(zhu菐n)鎻涢€熺巼: 鍒嗚鲸鐜�: 杓稿叆椤炲瀷: 淇″櫔姣�: 鎺ュ彛椤炲瀷: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰ㄦ牸: 灏佽 / 绠遍珨: |
| AD7357YRUZ | 鍔熻兘鎻忚堪:IC ADC DUAL14BIT 4.2MSPS 16TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯欐簴鍖呰:1 绯诲垪:- 浣嶆暩(sh霉):14 閲囨ǎ鐜囷紙姣忕锛�:83k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶锛屽苟鑱�(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:95mW 闆诲闆绘簮:闆� ± 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:閫氬瓟 灏佽/澶栨:28-DIP锛�0.600"锛�15.24mm锛� 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-PDIP 鍖呰:绠′欢 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:1 鍊嬪柈绔�锛岄洐妤� |
| AD7357YRUZ-500RL7 | 鍔熻兘鎻忚堪:IC ADC DUAL14BIT 4.2MSPS 16TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯欐簴鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:300k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:骞惰伅(li谩n) 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:75mW 闆诲闆绘簮:鍠浕婧� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:24-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:24-SOIC 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:1 鍊嬪柈绔�锛屽柈妤碉紱1 鍊嬪柈绔�锛岄洐妤� |
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