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KS0711 65COM/132SEG DRIVER & CONTROLLER FOR 4 G/S STN LCD
20
Preliminary
LCD DRIVING CIRCUIT
OSCILLATOR
This is a completely on-chip oscillator and its frequency is nearly independent of
V
DD
. This oscillator signal is used
in the voltage converter and display timing generation circuit.
DISPLAY TIMING GENERATOR CIRCUIT
This circuit generates some signals to be used in the LCD. The display clock CL generates a clock to the line
counter and a latch signal to the display data latch. The line address of the on-chip RAM is generated in
synchronization with the display clock (CL) and the 100-bit display data is latched by the display data latch circuit in
synchronization with the display clock. The display data which is read to the LCD driver is completely independent
of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M)
which enables the LCD driver to make an AC drive waveform, and also generates an internal common timing
signal and start signal to the common driver. 2-frame AC driver waveforms and the internal timing signal are shown
in Figure 6.
When KS0711 is used in multi-chip mode, the slave chip needs to receive the M, CL, DISP signals from the
master. Table 8 shows the M, CL, and DISP status.
DISPLAY DATA LATCH CIRCUIT
This latch circuit temporarily stores the output display data from the display data RAM to the LCD driver in each
instruction period. This latch circuit is controlled by the display ON / OFF, Reverse display ON / OFF and entire
display ON / OFF instructions, and the data in the display data RAM remains unchanged.
FRC (FRAME RATE CONTROL) AND PWM (PULSE WIDTH MODULATION) FUNCTION CIRCUIT
The KS0711 incorporates an FRC function and a PWM function circuit to display a four-level gray scale. The FRC
function and PWM utilize liquid crystal characteristics whose transmittance is changed by an effective value of
applied voltage. The KS0711 provides 4 4-bit palette-registers to assign the desired gray level. These registers are
set by the instructions and RESETB.
Table 8. Master and Slave Timing Signal Status
Operation Mode
Oscillator ON / OFF
M
CL
DISP
Master
ON (Internal clock used)
Output
Output
Output
OFF (External clock used)
Output
Input
Output
Slave
Input
Input
Input