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參數資料
| 型號： | KS0668 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER |
| 中文描述： | 6通道384位的TFT - LCD源驅動 |
| 文件頁數： | 17/19頁 |
| 文件大?。?/td> | 171K |
| 代理商： | KS0668 |
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
KS0668
17
AC CHARACTERISTICS
Table 6. AC Characteristics (Ta = -20 to 75
°
C, VDD1 = 2.7 to 3.6 V, VDD2 = 5.0 to 8.0 V, VSS1 = VSS2 = 0 V)
Parameter
Clock pulse width
Clock pulse low period
Clock pulse high period
Data setup time
Data hold time
Start pulse setup time
Start pulse hold time
DATPOL-CLK2 setup
time
DATPOL-CLK2 hold time
Start pulse delay time
Symbol
PWCLK
PWCLK (L)
PWCLK (H)
tSETUP1
tHOLD1
tSETUP2
tHOLD2
Condition
-
-
-
(1)
Min.
18
5
5
4 / 6
0 / 2
4 / 6
0 / 2
Typ.
-
-
-
-
-
-
-
Max.
-
-
-
-
-
-
-
Unit
(1)
(1)
(1)
tSETUP4
(1)
4 / 6
-
-
tHOLD4
tPLH1
(1)
0 / 2
-
-
-
-
CL = 20pF
12
ns
CLK1 setup time
tSETUP3
-
2
-
-
CLK2
period
Driver output delay time1
Driver output delay time2
CLK1 pulse high period
Data invalid period
Last data timing
CLK1 - CLK2 time
POL - CLK1 time
tPHL1
tPHL2
PWCLK1
tINV
tLDT
tCLK1 - CLK2
tPOL -CLK1
(2), (4)
-
-
-
-
-
5
10
2
(3), (4)
-
0.2
μ
s
DIO1 (2)
↑
→
CLK2
↑
-
CLK1
↑
→
CLK2
↑
POL
↑
or
↓
→
CLK1
↑
1
1
6
5
-
-
-
-
-
-
CLK2
period
ns
ns
NOTES:
1. Input condition (VIH = 0.6VDD1, VIL = 0.3VDD1 / VIH = 0.5VDD1, VIL = 0.5VDD1)
2. The value is specified when the drive voltage value reaches the target output voltage level of 90%
3. The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.
4. Yout Load Condition
VCOM = 0.5VDD2
10k
20k
20k
30pF
30pF
30pF
YOUT
Figure 5. Yout Load Condition
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