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參數(shù)資料
| 型號： | KS0666 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 6 BIT 384 CHANNEL RSDS TFT-LCD SOURCE DRIVER |
| 中文描述： | 6位384通道區(qū)特別職務(wù)隊(duì)的TFT - LCD源驅(qū)動 |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 190K |
| 代理商： | KS0666 |
KS0666
6 BIT 384 CHANNEL RSDS TFT–LCD SOURCE DRIVER
18
AC CHARACTERISTICS
Table 6. AC Characteristics (Ta = - 20 to 75
°
C, VDD2 = 7.0 to 10.5 V, VSS1 = VSS2 = 0 V)
Parameter
Clock pulse width
Clock pulse low period
Clock pulse high period
Data setup time
Data hold time
Start pulse setup time
Start pulse hold time
Start pulse delay time
DIO signal pulse width
CLK1 setup time
CLK1 high pulse width
Driver output delay time1
Driver output delay time2
Repair output delay time1
Repair output delay time2
Symbol
PWCLK
PWCLK(L)
PWCLK(H)
tSETUP1
tHOLD1
tSETUP2
tHOLD2
tPLH1
PWDIO
tSETUP3
PWCLK1
tPHL1
tPHL2
tPHL3
tPHL4
Condition
-
-
-
-
-
-
-
CL = 15pF
Min.
15
6
6
2
0
4
2
-
1CLKP
2CLKP
0.5
-
-
-
-
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
Max.
-
-
-
-
-
-
-
12
2CLKP
-
2
6
10
6
10
Unit
ns
-
-
CLKP
period
(1) (3)
(2) (3)
CL = 150pF
CL = 150pF
-
μ
s
Last data timing
tLDT
-
1CLKP
-
-
CLKP
period
CLK1-CLK2 time
POL-CLK1 time
CLK1-POL time
tCLK1-CLK2
tPOL-CLK1
tCLK1-POL
CLK1
↑
→
CLKP
↓
POL
↑
or
↓
→
CLK1
↑
CLK1
↓
→
POL
↑
or
↓
4
-
-
-
-
-
-
14
10
ns
NOTES:
1.
2.
3. Yout load condition (refer to Figure 4. Yout Load Condition)
The value is specified when the drive voltage value reaches the target output voltage level of 90%
The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.
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