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參數(shù)資料
| 型號： | KM736V695 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64Kx36-Bit Synchronous Pipelined Burst SRAM(64Kx36位同步流水線脈沖 靜態(tài) RAM) |
| 中文描述： | 64Kx36位同步流水線突發(fā)靜態(tài)存儲器（64Kx36位同步流水線脈沖靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 314K |
| 代理商： | KM736V695 |
PRELIMINARY
KM736V695/L
64Kx36 Synchronous SRAM
- 14 -
Rev 1.1
April 1997
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 64Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 64K depth to 128K depth without extra logic.
Data
Address
CLK
ADS
64-Bits
Microprocessor
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address
Data
ADV
ADSP
64Kx36
SPB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address
Data
ADV
ADSP
64Kx36
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:16]
A
[16]
A
[0:15]
A
[16]
A
[0:15]
I/O
[0:71]
* Please refer to attached timing diagram 2
Clock
ADSP
ADDRESS
[0:n]
Data Out
(Bank 0)
Bank 0 is selected by
CS
2
, and Bank 1 deselected by
CS
2
Q1-1
Q1-2
Q1-4
Q1-3
OE
Data Out
(Bank 1)
t
SS
t
SH
A1
A2
WRITE
CS
1
A
n+1
ADV
Q2-2
Q2-4
Q2-3
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
ADVH
t
OE
t
LZOE
t
HZC
Bank 0 is deselected by
CS
2
, and Bank 1 selected by
CS
2
t
CSS
t
CSH
t
CD
t
LZC
Q2-1
INTERLEAVE READ TIMING
(Refer to non-interleave write timing for interleave write timing)
Don
′
t Care
Undefined
*NOTES n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
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