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參數(shù)資料
| 型號： | KM736V587 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32Kx36-Bit Synchronous Burst SRAM(32Kx36位同步脈沖 靜態(tài) RAM) |
| 中文描述： | 32Kx36位同步突發(fā)靜態(tài)存儲器（32Kx36位同步脈沖靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 343K |
| 代理商： | KM736V587 |
PRELIMINARY
KM736V587
32Kx36 Synchronous SRAM
- 7 -
Rev 1.0
May 1997
AC TIMING CHARACTERISTICS
(T
A
=0 to 70
°
C, V
DD
=3.3V
±
5%)
NOTE
: 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
Parameter
Symbol
KM736V587-8
KM736V587-9
KM736V587-10
Unit
Min
Max
Min
Max
Min
Max
Cycle Time
t
CYC
12
-
12
-
15
-
ns
Clock Access Time
t
CD
-
8.5
-
9
-
10
ns
Output Enable to Data Valid
t
OE
-
4
-
4
-
5
ns
Clock High to Output Low-Z
t
LZC
4
-
4
-
6
-
ns
Output Hold from Clock High
t
OH
3
-
3
-
3
-
ns
Output Enable Low to Output Low-Z
t
LZOE
0
-
0
-
0
-
ns
Output Enable High to Output High-Z
t
HZOE
2
5
2
5
2
5
ns
Clock High to Output High-Z
t
HZC
-
5
-
5
-
6
ns
Clock High Pulse Width
t
CH
4
-
4
-
5
-
ns
Clock Low Pulse Width
t
CL
4
-
4
-
5
-
ns
Address Setup to Clock High
t
AS
2.5
-
2.5
-
2.5
-
ns
Address Status Setup to Clock High
t
SS
2.5
-
2.5
-
2.5
-
ns
Data Setup to Clock High
t
DS
2.5
-
2.5
-
2.5
-
ns
Write Setup to Clock High
t
WS
2.5
-
2.5
-
2.5
-
ns
Address/Advance Setup to Clock High
t
ADVS
2.5
-
2.5
-
2.5
-
ns
Chip Select Setup to Clock High
t
CSS
2.5
-
2.5
-
2.5
-
ns
Address Hold from Clock High
t
AH
0.5
-
0.5
-
0.5
-
ns
Address Status Hold from Clock High
t
SH
0.5
-
0.5
-
0.5
-
ns
Data Hold from Clock High
t
DH
0.5
-
0.5
-
0.5
-
ns
Write Hold from Clock High
t
WH
0.5
-
0.5
-
0.5
-
ns
Address Advance Hold from Clock High
t
ADVH
0.5
-
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
t
CSH
0.5
-
0.5
-
0.5
-
ns
ZZ High to Power Down
t
PDS
2
-
2
-
2
-
cycle
ZZ Low to Power Up
t
PUS
2
-
2
-
2
-
cycle
Output Load(A)
Output Load(B)
(for
tLZC
, t
LZOE
, t
HZOE
&
t
HZC
)
Dout
353
5pF*
+3.3V
319
* Including Scope and Jig Capacitance
Fig. 1
Dout
Z0=50
VL=1.5V
30pF*
RL=50
* Capacitive Load consists of all components of
the test environment.
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| KM736V687 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Kx36-Bit Synchronous Burst SRAM, 3.3V Power Datasheets for 100TQFP |
| KM736V687-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| KM736V687-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| KM736V687-9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| KM736V687A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Kx36 Synchronous SRAM |
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