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參數(shù)資料
| 型號： | KM736V587 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 32Kx36-Bit Synchronous Burst SRAM(32Kx36位同步脈沖 靜態(tài) RAM) |
| 中文描述： | 32Kx36位同步突發(fā)靜態(tài)存儲器（32Kx36位同步脈沖靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 343K |
| 代理商： | KM736V587 |
PRELIMINARY
KM736V587
32Kx36 Synchronous SRAM
- 14 -
Rev 1.0
May 1997
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 32Kx36 Synchronous Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 32K depth to 64K depth without extra logic.
Data
Address
CLK
ADS
Microprocessor
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address
Data
ADV
ADSP
32Kx36
SB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address
Data
ADV
ADSP
32Kx36
SB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:15]
A
[15]
A
[0:14]
A
[15]
A
[0:14]
I/O
[0:71]
64-bits
* Please refer to attached timing diagram 1
CLOCK
ADSP
ADDRESS
[0:n]
Data Out
(Bank 0)
INTERLEAVE READ TIMING
(Refer to non-interleave write timing for interleave write timing)
Bank 0 is selected by CS
2
, and Bank 1 deselected by CS
2
Q1-1
Q1-2
Q1-4
Q1-3
OE
Data Out
(Bank 1)
t
SS
t
SH
A1
A2
WRITE
CS
1
A
n+1
ADV
Q2-1
Q2-2
Q2-4
Q2-3
t
AS
t
AH
t
CSS
t
CSH
t
WS
t
WH
t
ADVS
t
ADVH
t
OE
t
LZOE
t
HZC
Bank 0 is deselected by CS
2
, and Bank 1 selected by CS
2
Don
′
t Care
Undefined
t
CD
t
LZC
*NOTES
n = 14 32K depth,
15 64K depth, 16 128K depth, 17 256K depth
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