參數(shù)資料
型號(hào)： KM732V596L
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 32Kx32 Synchronous SRAM
中文描述： 32Kx32同步SRAM
文件頁(yè)數(shù)： 2/16頁(yè)
文件大?。?/td> 498K
代理商： KM732V596L
PRELIMINARY
Rev 1.0
KM732V596A/L
32Kx32 Synchronous SRAM
- 2 -
May 1997
WEc
WEd
OE
ZZ
32Kx32-Bit Synchronous Pipelined Burst SRAM
FEATURES
Synchronous Operation.
2 Stage Pipelined operation with 4 Burst.
On-Chip Address Counter.
Write Self-Timed Cycle.
On-Chip Address and Control Registers.
V
DD
=3.3V-5%/+10% Power Supply for 3.3V I/O.
V
DD
=3.3V
±
5% Power Supply for 2.5V I/O.
I/O Supply Voltage : 3.3V-5%/+10% for 3.3V I/O
or 2.5V+0.4V/-0.13V for 2.5V I/O
5V Tolerant Inputs except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
LBO Pin allows a choice of either a interleaved burst or a
linear burst.
Three Chip Enables for simple depth expansion with No Data
Contention ; 2cycle Enable, 1cycle Disable.
TTL-Level Three-State Output.
100-TOFP-1420A
The KM732V596A/L is a 1,048,576 bit Synchronous Static
Random Access Memory designed for high performance sec-
ond level cache of Pentium and Power PC based Mobile Sys-
tem.
It is organized as 32K words of 32 bits and integrates address
and control registers, a 2-bit burst address counter and added
some new functions for high performance cache RAM applica-
tions; GW, BW, LBO, ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system
′
s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The KM732V596A/L is fabricated using SAMSUNG
′
s high per-
formance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
GENERAL DESCRIPTION
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
ADSP
CS
1
CS
2
CS
2
GW
BW
WEa
WEb
DQa
0
~ DQd
7
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
32Kx32
MEMORY
ARRAY
ADDRESS
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
DATA-IN
REGISTER
BUFFER
C
R
C
R
A
′
0
~A
′
1
A
0
~ A
1
A
2
~A
14
A
0
~A
14
FAST ACCESS TIMES
Parameter
Symbol
-13
-15
Unit
Cycle Time
t
CYC
13
15
ns
Clock Access Time
t
CD
7
8
ns
Output Enable Access Time
t
OE
6
7
ns
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