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參數(shù)資料
| 型號(hào)： | KM718V990 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx18 Synchronous SRAM(512Kx18位同步靜態(tài) RAM) |
| 中文描述： | 512Kx18同步SRAM（512Kx18位同步靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 15/17頁 |
| 文件大小： | 365K |
| 代理商： | KM718V990 |
PRELIMINARY
KM718V990
256Kx36 & 512Kx18 Synchronous SRAM
- 15 -
Rev 0.4
Sep. 1998
KM736V890
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 256Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
Data
Address
CLK
ADS
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV
ADSP
256Kx36
SPB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV
ADSP
256Kx36
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:18]
A
[18]
A
[0:17]
A
[18]
A
[0:17]
I/O
[0:71]
Microprocessor
*NOTES
n = 14 32K depth
15 64K depth
16 128K depth
17 256K depth
18 512K depth
19 1024K depth
Clock
ADSP
ADDRESS
[0:n*]
Data Out
(Bank 0)
OE
Data Out
(Bank 1)
WRITE
CS
1
A
n+1*
ADV
INTERLEAVE READ TIMING
(Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Bank 0 is selected by
CS
2
, and Bank 1 deselected by
CS
2
Q1-1
Q1-2
Q1-4
Q1-3
t
SS
t
SH
A1
Q2-2
Q2-4
Q2-3
t
WS
t
WH
t
ADVS
t
ADVH
t
OE
t
LZOE
t
HZC
Bank 0 is deselected by
CS
2
, and Bank 1 selected by
CS
2
t
CSS
t
CSH
t
CD
t
LZC
Q2-1
A2
t
AS
t
AH
Don
′
t Care
Undefined
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