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參數(shù)資料
| 型號(hào)： | KM718V949 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx18-Bit No Turnaround SRAM(512Kx18位數(shù)據(jù)流無返回靜態(tài) RAM) |
| 中文描述： | 512Kx18位無轉(zhuǎn)機(jī)的SRAM（512Kx18位數(shù)據(jù)流無返回靜態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 9/17頁(yè) |
| 文件大小： | 276K |
| 代理商： | KM718V949 |
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PRELIMINARY
KM736V849
KM718V949
256Kx36 & 512Kx18 Pipelined N
t
RAM
TM
- 9 -
Rev 0.1
Aug. 1998
DC ELECTRICAL CHARACTERISTICS
(V
DD
=3.3V+0.165V/-0.165V, T
A
=0
°
C to +70
°
C)
* V
IL
(Min)=-2.0(Pulse Width
≤
t
CYC
/
2)
** V
IH
(Max)=4.6(Pulse Width
≤
t
CYC
/
2)
** In Case of I/O Pins, the Max. V
IH
=V
DDQ
+0.5V
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
I
IL
V
DD
=Max ; V
IN
=V
SS
to V
DD
-2
+2
μ
A
μ
A
Output Leakage Current
I
OL
Output Disabled,
-2
+2
Operating Current
I
CC
V
DD
=Max I
OUT
=-0mA
Cycle Time
≥
t
CYC
Min
-67
-
420
mA
-75
-
370
-10
-
300
Standby Current
I
SB
Device deselected, I
OUT
=0mA,
ZZ
≤
V
IL
, f=Max, All Inputs
≤
0.2V or
≥
V
DD
-0.2V
-67
-
80
mA
-75
-
70
-10
-
60
I
SB1
Device deselected, I
OUT
=0mA, ZZ
≤
0.2V,
f=0, All Inputs=fixed (V
DD
-0.2V or 0.2V)
-
20
mA
I
SB2
Device deselected, I
OUT
=0mA, ZZ
≥
V
DD
-0.2V,
f=Max, All Inputs
≤
V
IL
or
≥
V
IH
-
20
mA
Output Low Voltage(3.3V I/O)
V
OL
I
OL
=8.0mA
-
0.4
V
Output High Voltage(3.3V I/O)
V
OH
I
OH
=-4.0mA
2.4
-
V
Output Low Voltage(2.5V I/O)
V
OL
I
OL
=1.0mA
-
0.2
V
Output High Voltage(2.5V I/O)
V
OH
I
OH
=-1.0mA
2.0
-
V
Input Low Voltage(3.3V I/O)
V
IL
-0.3*
0.8
V
Input High Voltage(3.3V I/O)
V
IH
2.0
V
DD
+0.5**
V
Input Low Voltage(2.5V I/O)
V
IL
-0.3*
0.7
V
Input High Voltage(2.5V I/O)
V
IH
1.7
V
DD
+0.5**
V
(V
DD
=3.3V+0.165V/-0.165V,V
DDQ
=3.3V+0.165/-0.165V or V
DD
=3.3V+0.165V/-0.165V,V
DDQ
=2.5V+0.4V/-0.125V, T
A
=0to70
°
C)
Parameter
TEST CONDITIONS
Value
Input Pulse Level(for 3.3V I/O)
0 to 3.0V
Input Pulse Level(for 2.5V I/O)
0 to 2.5V
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)
1.0V/ns
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)
1.0V/ns
Input and Output Timing Reference Levels for 3.3V I/O
1.5V
Input and Output Timing Reference Levels for 2.5V I/O
V
DDQ
/2
Output Load
See Fig. 1
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