
PRELIMINARY
KM736V849
KM718V949
256Kx36 & 512Kx18 Pipelined N
t
RAM
TM
- 2 -
Rev 0.1
Aug. 1998
256Kx36 & 512Kx18-Bit N
t
RAM
TM
The KM736V849 and KM718V949 are 9,437,184 bits Synchro-
nous Static SRAMs.
The N
t
RAM
TM
, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incomming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge trigered output register and then released to
the output bufferes at the next rising edge of clock.
The KM736V849 and KM718V949 are implemented with SAM-
SUNG
′
s high performance CMOS technology and is available
in 100pin TQFP packages. Multiple power and ground pins
minimize ground bounce.
GENERAL DESCRIPTION
FEATURES
3.3V+0.165V/-0.165V Power Supply.
I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
Byte Writable Function.
Enable clock and suspend operation.
Single READ/WRITE control pin.
Self-Timed Write Cycle.
Three Chip Enable for simple depth expansion with no data
contention
Α
interleaved burst or a linear burst mode.
Asynchronous output enable control.
Power Down mode.
LOGIC BLOCK DIAGRAM
FAST ACCESS TIMES
Parameter
Symbol
-67 -75 -10 Unit
Cycle Time
t
CYC
6.7
7.5
10
ns
Clock Access Time
t
CD
3.8
4.0
5.0
ns
Output Enable Access Time
t
OE
3.8
4.0
5.0
ns
WE
BW
(x=a,b,c,d or a,b)
CLK
CKE
CS
1
CS
2
CS
2
ADV
OE
ZZ
DQa
~ DQd
or
DQa
0
~ DQb
8
DQPa ~ DQPd
ADDRESS
REGISTER
ADDRESS
REGISTER
C
L
A
′
0
~A
′
1
36 or 18
OUTPUT
REGISTER
BUFFER
DATA-IN
REGISTER
DATA-IN
REGISTER
K
K
K
BURST
ADDRESS
COUNTER
WRITE
ADDRESS
REGISTER
WRITE
CONTROL
LOGIC
C
R
K
A [0:17]or
A [0:18]
LBO
A
0
~A
1
A
2
~A
17
or
A
2
~A
18
256Kx36/512Kx18
MEMORY
ARRAY
N
t
RAM
TM
and No Turnaround RAM are trademarks of Samsung Electronics Co.,Ltd.