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參數(shù)資料
| 型號： | KM718V949 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx18-Bit No Turnaround SRAM(512Kx18位數(shù)據(jù)流無返回靜態(tài) RAM) |
| 中文描述： | 512Kx18位無轉(zhuǎn)機(jī)的SRAM（512Kx18位數(shù)據(jù)流無返回靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 276K |
| 代理商： | KM718V949 |
PRELIMINARY
KM736V849
KM718V949
256Kx36 & 512Kx18 Pipelined N
t
RAM
TM
- 11 -
Rev 0.1
Aug. 1998
SLEEP MODE
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SB2
. The duration of
SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, I
SB2
is guaranteed after the time t
ZZI
is met. Any operation pending when entering SLEEP
MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-
ing operations are completed. similarly, when exiting SLEEP MODE during t
PUS
, only a DESELECT or READ cycle should be given
while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
Current during SLEEP MODE
ZZ
≥
V
IH
I
SB2
10
mA
ZZ active to input ignored
t
PDS
2
cycle
ZZ inactive to input sampled
ZZ active to SLEEP current
t
PUS
2
cycle
t
ZZI
2
cycle
ZZ inactive to exit SLEEP current
t
RZZI
0
K
t
PDS
ZZ setup cycle
t
RZZI
ZZ
Isupply
All inputs
(except ZZ)
Outputs
(Q)
t
ZZI
t
PUS
ZZ recovery cycle
Deselect or Read Only
High-Z
DON
′
T CARE
I
SB2
SLEEP MODE WAVEFORM
Normal
operation
cycle
Deselect or Read Only
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