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參數(shù)資料
| 型號： | KM718V895 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx18 Synchronous SRAM(256Kx18位同步靜態(tài) RAM) |
| 中文描述： | 256Kx18同步SRAM（256Kx18位同步靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 314K |
| 代理商： | KM718V895 |
KM718V895
256Kx18 Synchronous SRAM
- 7 -
Rev 1.0
May 1998
Output Load(B), (2.5V I/O)
(for t
LZC
, t
LZOE
, t
HZOE
& t
HZC
)
Dout
1538
5pF*
+2.5V
1667
* Including Scope and Jig Capacitance
Fig. 1
TEST CONDITIONS
(T
A
=0 to 70
°
C, V
DD
=3.3V+0.3V/-0.165V, V
DDQ
=2.5V+0.4V/-0.13V, unless otherwise specified)
Parameter
Value
Input Pulse Level
0 to 2.5V
Input Rise and Fall Time(Measured at 0.3V and 2.1V)
2ns
Input and Output Timing Reference Levels
V
DDQ
/2
Output Load
See Fig. 1
DC ELECTRICAL CHARACTERISTICS
(T
A
=0 to 70
°
C, V
DD
=3.3V+0.3V/-0.165V, V
DDQ
=2.5V+0.4V/-0.13V)
* V
IL
(Min)=-2.0(Pulse Width
≤
t
CYC
/
2)
** V
IH
(Max)=4.6(Pulse Width
≤
t
CYC
/
2)
** In Case of I/O Pins, the Max. V
IH
=V
DDQ
+0.5V
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current(except ZZ)
I
IL
V
DD
=Max ; V
IN
=V
SS
to V
DD
-2
+2
μ
A
μ
A
Output Leakage Current
I
OL
Output Disabled, V
OUT
=V
SS
to V
DDQ
-2
+2
Operating Current
I
CC
Device Selected, I
OUT
=0mA,
ZZ
≤
V
IL
, All Inputs=V
IL
or V
IH
Cycle Time
≥
t
CYC
min
-60
-
425
mA
-67
-
400
-72
-
375
-85
-
350
Standby Current
I
SB
Device deselected, I
OUT
=0mA,
ZZ
≤
V
IL
, f=Max,
All Inputs
≤
0.2V or
≥
V
DD
-0.2V
-60
-
130
mA
-67
-
120
-72
-
110
-85
-
110
I
SB1
Device deselected, I
OUT
=0mA,
ZZ
≤
0.2V, f = 0,
All Inputs=fixed (V
DD
-0.2V or 0.2V)
-
30
mA
I
SB2
Device deselected, I
OUT
=0mA,
ZZ
≥
V
DD
-0.2V, f=Max,
All Inputs
≤
V
IL
or
≥
V
IH
-
30
mA
Output Low Voltage
V
OL
I
OL
=1.0mA
-
0.4
V
Output High Voltage
V
OH
I
OH
=-1.0mA
2.0
-
V
Input Low Voltage
V
IL
-0.3*
0.7
V
Input High Voltage
V
IH
1.7
V
DD
+0.5**
V
Output Load(A)
Dout
Z0=50
V
DDQ
/2
* Capacitive Load consists of all components of
the test environment.
30pF*
RL=50
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