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參數(shù)資料
| 型號： | KFM1G16Q2M-DED5 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | MuxOneNAND FLASH MEMORY |
| 中文描述： | MuxOneNAND閃存 |
| 文件頁數(shù)： | 74/124頁 |
| 文件大?。?/td> | 1550K |
| 代理商： | KFM1G16Q2M-DED5 |
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MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
FLASH MEMORY
74
Upon power up, the number of initial clock cycles from Valid Address (/AVD) to initial data defaults to four clocks.
The number of clock cycles (n) which are inserted after the clock which is latching the address. The host can read the first data with
the (n+1)th rising edge.
The number of total initial access cycles is programmable from three to seven cycles. After the number of programmed burst clock
cycles is reached, the rising edge of the next clock cycle triggers the next burst data.
Four Clock Burst Read Latency (default condition)
3.7.3 Handshaking Operation
The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine
when the initial word of burst data is ready to be read.
To set the number of initial cycles for optimal burst mode, the host should use the programmable burst read latency configuration (see
Section 2.8.19, "System Configuration1 Register").
The rising edge of RDY which is derived at the same cycle of data fetch clock indicates the initial word of valid burst data.
3.7.2.3 Programmable Burst Read Latency Operation
See Timing Diagrams 6.1 and 6.2
t
IAA
Hi-Z
CE
CLK
AVD
OE
RDY
≈
≈
t
RDYA
A/DQ0:
A/DQ15
D6
D7
D0
D1
D2
D3
D7
D0
Hi-Z
≈
≈
≈
Valid
Address
-1
0
1
2
3
t
BA
Rising edge of the clock cycle following last read latency
triggers next burst data
t
RDYS
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KFM1G16Q2M-DED6 | MuxOneNAND FLASH MEMORY |
| KFN2G16Q2M-DEB6 | MuxOneNAND FLASH MEMORY |
| KFN1G16Q2M-DED5 | MuxOneNAND FLASH MEMORY |
| KFN1G16Q2M-DED6 | MuxOneNAND FLASH MEMORY |
| KFM2G16Q2M-DED5 | MuxOneNAND FLASH MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KFM1G16Q2M-DED6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:MuxOneNAND FLASH MEMORY |
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