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參數(shù)資料
| 型號： | KFM1G16Q2M-DEB6 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | MuxOneNAND FLASH MEMORY |
| 中文描述： | MuxOneNAND閃存 |
| 文件頁數(shù)： | 12/124頁 |
| 文件大?。?/td> | 1550K |
| 代理商： | KFM1G16Q2M-DEB6 |
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MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
FLASH MEMORY
12
NOTE:
Do not leave power supply(Vcc-Core/Vcc-IO, V
SS
) disconnected.
Pin Name
Type
Name and Description
Host Interface
ADQ15~ADQ0
I/O
Multiplexed Address/Data bus
- Inputs for addresses during read operation, which are for addressing BufferRAM & Register.
- Inputs data during program and commands for all operations, outputs data during memory array/
register read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are disabled.
INT
O
Interrupt
Notifies the Host when a command is completed. It is open drain output with internal
resistor(~50kohms). After power-up, it is at hi-z condition. Once IOBE is set to 1,
it does not float to hi-z condition even when the chip is deselected or when outputs are disabled.
RDY
O
Ready
Indicates data valid in synchronous read modes and is activated while CE is low
CLK
I
Clock
CLK synchronizes the device to the system bus frequency in synchronous read mode.
The first rising edge of CLK in conjunction with AVD low latches address input.
WE
I
Write Enable
WE controls writes to the bufferRAM and registers. Datas are latched on the WE pulse’s rising edge
AVD
I
Address Valid Detect
Indicates valid address presence on address inputs. During asynchronous read operation, all addresses
are latched on AVD’s rising edge, and during synchronous read operation, all addresses are latched on
CLK’s rising edge while AVD is held low for one clock cycle.
> Low : for asynchronous mode, indicates valid address ;for burst mode,
causes starting address to be latched on rising edge on CLK
> High : device ignores address inputs
RP
I
Reset Pin
When low, RP resets internal operation of MuxOneNAND. RP status is don’t care during power-up
and bootloading.
CE
I
Chip Enable
CE-low activates internal control logic, and CE-high deselects the device, places it in standby state,
and places A/DQ in Hi-Z
OE
I
Output Enable
OE-low enables the device’s output data buffers during a read cycle.
Power Supply
V
CC
-Core
/ Vcc
Power for MuxOneNAND Core
This is the power supply for MuxOneNAND Core.
V
CC
-IO
/ Vccq
Power for MuxOneNAND I/O
This is the power supply for MuxOneNAND I/O
Vcc-IO / Vccq is internally separated from Vcc-Core / Vcc.
V
SS
Ground for MuxOneNAND
etc.
DNU
Do Not Use
Leave it disconnected. These pins are used for testing.
NC
No Connection
Lead is not internally connected.
2.4 Pin Description
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