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MuxOneNAND512(KFM1216Q2M)
FLASH MEMORY
7
Document Title
MuxOneNAND
0. Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
Revision No.
1.1
1.2
1.3
Remark
Final
Final
Draft Date
Oct. 19, 2004
Dec. 8, 2004
Jun. 15, 2005
History
1. Corrected the errata
2. Deleted BootRAM Lock/Unlock commands
3. Revised Cold Reset timing diagram
4. Added CE and RDY in Warm Reset diagram
5. Revised Dual Operation description
6. Revised Icc4, Icc5 test condition
7. Revised OTP/Lock time from 300/600ns to 600/1000ns
8. Excluded Commercial Temperature range
9. Revesed the timing reference of Reset and Performance from INT pin to
INT bit
1. Corrected the errata
2. Added Controller Status Regiseter values of OTP Erase
3. Revised tRD2 typical value from 75us to 85us
1. Added Copyright Notice in the beginning
2. Corrected Errata
3. Revised INT pin description
4. Removed "or erase case, refer to the table 3" from descriptions of WB, EB
5. Added OTP erase case NOTE
6. Revised case definitions of Interrupt Status Register
7. Added a NOTE to Command register
8. Added ECClogSector Information table
9. Removed ’data unit based data handling’ from description of Device
Operation
10. Revised description on Warm/Hot/NAND Flash Core Reset
11. Revised Warm Reset Timing
12. Revised description for 4-, 8-, 16-, 32-Word Linear Burst Mode
13. Added Copy-Back Program Operation with Random Data Input
14. Revised OTP operation description
15. Restored earlier text for OTP Programming
16. Added supplemental explanation for ECC Operation
17. Replaced "read" with "load" in ECC bypass
18. Removed redundant sentance from ECC Bypass Operation
19. Added technical note for Boot Sequence
20. Added technical note for INT pin connection guide