參數(shù)資料
型號(hào): KFM1216Q2M-DED
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: FLASH MEMORY
中文描述: 閃存
文件頁數(shù): 80/88頁
文件大小: 1150K
代理商: KFM1216Q2M-DED
MuxOneNAND512(KFM1216Q2M)
FLASH MEMORY
80
SWITCHING WAVEFORMS
10.3 Asynchronous Read
NOTE:
1. If OE is disabled before CE is disabled, the output will go to high-z by t
OEZ
(max. 17ns).
If CE is disabled before OE is disabled, the output will go to high-z by t
CEZ
(max. 20ns).
If CE and OE are disabled at the same time, the output will go to high-z by t
OEZ
(max. 17ns).
These parameters are not 100% tested.
Parameter
Symbol
Min
Max
Unit
Access Time from CE Low
t
CE
-
76
ns
Asynchronous Access Time from AVD Low
t
AA
-
76
ns
Asynchronous Access Time from address valid
t
ACC
-
76
ns
Read Cycle Time
t
RC
76
-
ns
AVD Low Time
t
AVDP
12
-
ns
Address Setup to rising edge of AVD
t
AAVDS
5
-
ns
Address Hold from rising edge of AVD
t
AAVDH
7
-
ns
Output Enable to Output Valid
t
OE
-
20
ns
CE Setup to AVD falling edge
t
CA
0
-
ns
CE Disable to Output & RDY High Z
1)
t
CEZ
-
20
ns
OE Disable to Output & RDY High Z
1)
t
OEZ
-
17
ns
AVD High to OE Low
t
AVDO
0
-
ns
CE low to RDY valid
t
CER
-
15
ns
WE Disable to AVD Enable
t
WEA
15
-
ns
Case 1 : Valid Address Transition occurs before AVD is driven to Low
NOTE:
VA=Valid Read Address, RD=Read Data.
Figure 27. Asynchronous Read Mode
t
OE
Valid RD
t
CE
t
OEZ
t
AAVDH
t
AVDP
t
AA
t
AAVDS
CE
OE
WE
A/DQ0:
A/DQ15
AVD
Hi-Z
Hi-Z
RDY
t
RC
t
WEA
t
CA
t
CEZ
t
CER
t
AVDO
Hi-Z
VA
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