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參數(shù)資料
| 型號(hào)： | K4S28323LF-NR1L |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA |
| 中文描述： | 100萬(wàn)x 32Bit的× 4銀行在90FBGA移動(dòng)SDRAM |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 141K |
| 代理商： | K4S28323LF-NR1L |
K4S28323LF - F(H)E/N/S/C/L/R
February 2004
Mobile-SDRAM
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
NOTES :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Parameter
Symbol
- 60
- 75
-1H
-1L
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
t
CC
6.0
1000
7.5
1000
9.5
1000
9.5
1000
ns
1
CAS latency=2
t
CC
-
9.5
9.5
12
CAS latency=1
t
CC
-
-
-
25
CLK to valid output delay
CAS latency=3
t
SAC
5.4
6
7
7
ns
1,2
CAS latency=2
t
SAC
-
7
7
8
CAS latency=1
t
SAC
-
-
-
20
Output data hold time
CAS latency=3
t
OH
2.5
2.5
2.5
2.5
ns
2
CAS latency=2
t
OH
-
2.5
2.5
2.5
CAS latency=1
t
OH
-
-
-
2.5
CLK high pulse width
t
CH
2.5
2.5
3
3
ns
3
CLK low pulse width
t
CL
2.5
2.5
3
3
ns
3
Input setup time
t
SS
2.0
2.0
2.5
2.5
ns
3
Input hold time
t
SH
1.0
1.0
1.5
1.5
ns
3
CLK to output in Low-Z
t
SLZ
1
1
1
1
ns
2
CLK to output in Hi-Z
CAS latency=3
t
SHZ
5.4
6
7
7
ns
CAS latency=2
-
7
7
8
CAS latency=1
-
-
-
20
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