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參數(shù)資料
| 型號： | K4J52324QC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Mbit GDDR3 SDRAM |
| 中文描述： | 512MB的GDDR3 SDRAM的 |
| 文件頁數(shù)： | 48/57頁 |
| 文件大?。?/td> | 1246K |
| 代理商： | K4J52324QC |
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- 48 -
Rev 1.0 (Mar 2005)
512M GDDR3 SDRAM
K4J52324QC-B
Read w/ Auto- : Starts with registration of an READ command with auto precharge enabled and ends
Precharge Enabled when tRP has been met. Once t
RP
is met, the bank will be in the idle state.
Write w/ Auto- : Starts with registration of a WRITE command with auto precharge enabled and ends
Precharge Enabled when t
RP
has been met. Once t
RP
is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command ; COMMAND INHIBIT or NOP commands
must be applied on each positive clock edge during these states.
Refreshing : Starts with registration of an AUTO REFRESH command and ends when t
RC
is met.
Once t
RC
is met, the DDR2(x32) will be in the all banks idle state.
Accessing Mode : Starts with registration of a LOAD MODE REGISTER command and ends when t
MRD
has been met. Once t
MRD
is met, the GDDR3(x32) SDRAM will be in the all banks idle state.
Precharge All : Starts with registration of a PRECHARGE ALL command and ends when t
RP
is met.
Once t
RP
is met, all banks will be in the idle state.
READ or WRITE : Starts with registration of the ACTIVE command and ends the last valid data nibble.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific ; If multiple banks are to be precharged, each must be in a valid state for precharging.
9. Left blank
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled
and READs or WRITEs with auto precharge disabled.
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst.
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| K4J52324QC-BC14 | 512Mbit GDDR3 SDRAM |
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| K4J52324QC-BC20 | 512Mbit GDDR3 SDRAM |
| K4J52324QC-BJ12 | 512Mbit GDDR3 SDRAM |
| K4J52324QC-BJ14 | 512Mbit GDDR3 SDRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| K4J52324QC-AC20000 | 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC - Trays |
| K4J52324QC-BC14 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-BC14000 | 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC LEAD PART 10W - Trays |
| K4J52324QC-BC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-BC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
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