- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374275 > K4J52324QC (SAMSUNG SEMICONDUCTOR CO. LTD.) 512Mbit GDDR3 SDRAM PDF資料下載
參數(shù)資料
| 型號： | K4J52324QC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Mbit GDDR3 SDRAM |
| 中文描述： | 512MB的GDDR3 SDRAM的 |
| 文件頁數(shù)： | 16/57頁 |
| 文件大小： | 1246K |
| 代理商： | K4J52324QC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁
- 16 -
Rev 1.0 (Mar 2005)
512M GDDR3 SDRAM
K4J52324QC-B
The extended mode register stores the data output driver strength and on-die termination options. The
extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR3
SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode regis-
ter). The state of address pins A0 ~ A11 and BA0,BA1,BA2 in the same cycle as CS, RAS, CAS and WE
going low are written in the extended mode register. The minimum clock cycles specified as tMRD are required
to complete the write operation in the extended mode register. 4 kinds of the output driver strength are sup-
ported by EMRS (A1, A0) code. The mode register contents can be changed using the same command and
clock cycle requirements during operation as long as all banks are in the idle state. "High" on BA0 is used for
EMRS. Refer to the table for specific codes.
EXTENDED MODE REGISTER SET(EMRS)
BA
2
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DLL
A
6
0
1
DLL
Enable
Disable
Additive Latency
A
8
0
1
AL
0
1
RFU
0
1
Term
ID
RON
AL
tWR
DLL
tWR
Termination
Driver Strength
BA
1
0
0
BA
0
0
1
A
n
~ A
0
MRS
EMRS
ADDR/CMD Termination
A
11
0
1
Termination
Default
Half of deafult
Vendor ID
A
10
0
1
Vendor ID
Off
On
tWR
A
7
0
0
0
0
1
1
1
1
A
5
0
0
1
1
0
0
1
1
A
4
0
1
0
1
0
1
0
1
tWR
11
13
5
6
7
8
9
10
Drive Strength
A
1
0
0
1
1
A
0
0
1
0
1
Driver Strength
Autocal
30
40
50
Data
Termination
A
3
A
2
Termination
0
0
ODT Disabled
*1
Reserved
ZQ/4
ZQ/2
0
1
1
1
0
1
* ZQ : Resistor connection pin for On-die termination
RFU(Reserved for future use) should stay
"0" during EMRS cycle
* 1 : ALL ODT will be disabled
Default value is determined by
CKE status at the rising edge of
RESET during power-up
Ron of Pull-up
A
9
RON
0
40
1
60
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4J52324QC-BC14 | 512Mbit GDDR3 SDRAM |
| K4J52324QC-BC16 | 512Mbit GDDR3 SDRAM |
| K4J52324QC-BC20 | 512Mbit GDDR3 SDRAM |
| K4J52324QC-BJ12 | 512Mbit GDDR3 SDRAM |
| K4J52324QC-BJ14 | 512Mbit GDDR3 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4J52324QC-AC20000 | 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC - Trays |
| K4J52324QC-BC14 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-BC14000 | 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC LEAD PART 10W - Trays |
| K4J52324QC-BC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-BC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。