參數(shù)資料
型號： K4J52324QC-BJ14
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 512Mbit GDDR3 SDRAM
中文描述： 512MB的GDDR3 SDRAM的
文件頁數(shù)： 51/57頁
文件大?。?/td> 1246K
代理商： K4J52324QC-BJ14
- 51 -
Rev 1.0 (Mar 2005)
512M GDDR3 SDRAM
K4J52324QC-B
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure periods may affect reliability.
POWER & DC OPERATING CONDITIONS
Note :
Recommended operating conditions (Voltage referenced to 0
°
C
≤
Tc
≤
85°
C)
Note : 1.Under all conditions, VDDQ must be less than or equal to VDD.
3. VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on
VREF may not exceed + 2 percent of the DC value. Thus, from 70% of VDDQ, VREF is allowed + 25mV for DC error and an additional +25mV
for AC noise.
4. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain
a valid level. The inputs require the AC value to be achieved during signal transition edge and the driver should achieve the same slew rate
through the AC values.
5. Input and output slew rate =3V/ns. If the input slew rate is less than 3V/ns, input timing may be compromised. All slew rate are measured between
Vih and Vil. DQ and DM input slew rate must not deviate from DQS by more than 10%. If the DQ,DM and DQS slew rate is less than 3V/ns,
timing is longer than referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points.
6. VIH overshoot : VIH(max) = VDDQ + 0.5V for a pulse width
≤
500ps and the pulse width can not be greater than 1/3 of the cycle rate.
VIL undershoot : VIL(min)=0.0V for a pulse width
≤
500ps and the pulse width can not be greater than 1/3 of the cycle rate.
7. K4J52324QC-BJ**
8. K4J52324QC-BC**
Parameter
Symbol
Min
Typ
Max
Unit
Note
Device Supply voltage
V
DD
1.9
2.0
2.1
V
1,7
Output Supply voltage
V
DDQ
1.9
2.0
2.1
V
1,7
Device Supply voltage
V
DD
1.7
1.8
1.9
V
1,8
Output Supply voltage
V
DDQ
1.7
1.8
1.9
V
1,8
Reference voltage
V
REF
0.69*V
DDQ
-
0.71*V
DDQ
V
3
DC Input logic high voltage
V
IH (DC)
V
REF
+0.15
-
-
V
4
DC Input logic low voltage
V
IL (DC)
-
-
V
REF
-0.15
V
4
Output logic low voltage
V
OL(DC)
-
-
0.76
V
AC Input logic high voltage
V
IH(AC)
V
REF
+0.25
-
-
V
4,5,6
AC Input logic low voltage
V
IL(AC)
-
-
V
REF
-0.25
V
4,5,6
Input leakage current
Any input 0V-<V
IN
-< V
DDQ
(All other pins not under test = 0V)
I
I
-5
-
5
uA
Output leakage current
(DQs are disabled ; 0V-<V
OUT
-< V
DDQ
)
I
IOZ
-5
-
5
uA
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.5 ~ V
DDQ
+ 0.5V
V
Voltage on V
DD
supply relative to Vss
V
DD
-0.5 ~ 2.5
V
Voltage on V
DDQ
supply relative to Vss
V
DDQ
-0.5 ~ 2.5
V
MAX Junction Temperature
T
J
+125
°
C
Storage temperature
T
STG
-55 ~ +150
°
C
Power dissipation
P
D
TBD
W
Short Circuit Output Current
I
OS
50
mA
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