參數(shù)資料
型號: K4J52324QC-BJ14
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512Mbit GDDR3 SDRAM
中文描述: 512MB的GDDR3 SDRAM的
文件頁數(shù): 30/57頁
文件大小: 1246K
代理商: K4J52324QC-BJ14
- 30 -
Rev 1.0 (Mar 2005)
512M GDDR3 SDRAM
K4J52324QC-B
T0
T1
T2
T2n
T3
T3n
T4
CK#
CK
RDQS
1.6
DQ(Last data valid)
DQ(First data no longer valid)
All DQs and RDQS, collectively
5
t
CH
t
DQSQ2
(MAX)
t
DQSQ2
(MIN)
t
CH
T2
T2n
T3
T3n
T2
T2n
T3
T3n
T2
T2n
T3
T3n
t
DQSQ2
(MAX)
t
DQSQ2
(MIN)
t
DQSH4
t
DQSH4
t
DV4
t
DV4
t
DV4
t
DV4
Data Output Timing (1) - t
DQSQ
, t
QH
and Data Valid Window
Data Output Timing (2) - t
DQSQ
, t
QH
and Data Valid Window
T0
T1
T2
T2n
T3
T3n
T4
CK#
CK
RDQS
1.6
All DQs and RDQS, collectively
5
T2
T2n
T3
T3n
t
DQSH4
t
DQSH4
T2
T2n
T3
T3n
t
AC
(MAX)
t
DQSH4
t
DQSH4
t
AC
(MIN)
All DQs and RDQS, collectively
5
RDQS
1.6
t
CH
t
CH
Note :
1. t
DQSQ
represents the skew between the 8 DQ lines and the respective RDQS pin.
2. t
DQSQ
is derived at each RDQS clock edge and is not cumulative over time and begins with first DQ transition and ends
with the last valid transition of DQs.
3. t
AC
is show in the nominal case
4. t
DQHP
is the lesser of tDQSL or tDQSH strobe transition collectively when a bank is active.
5. The data valid window is derived for each RDQS transitions and is defined by t
DV
.
6. There are 4 RDQS pins for this device with RDQS0 in relation to DQ0-DQ7, RDQS1 in relation DQ8-DQ15, RDQS2 in
relation to DQ16-24 and RDQS3 in relation to DQ25-DQ31.
7. This diagram only represents one of the four byte lanes.
8. t
AC
represents the relationship between DQ, RDQS to the crossing of CK and /CK.
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