參數(shù)資料
型號： K4J52324QC-BJ14
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 512Mbit GDDR3 SDRAM
中文描述： 512MB的GDDR3 SDRAM的
文件頁數(shù)： 15/57頁
文件大小： 1246K
代理商： K4J52324QC-BJ14
- 15 -
Rev 1.0 (Mar 2005)
512M GDDR3 SDRAM
K4J52324QC-B
TEST MODE
The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 set to zero, and bits A0-A6 and A8-
A11 set to the desired values. Test mode is entered by issuing a MODE REGISTER SET command with bit A7 set to one, and bits A0-
A6 and A8-A11 set to the desired values. Test mode functions are specific to each Dram Manufacturer and its exact functions are hidden
from the user.
DLL RESET
The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A7 set to zero, and bits A0-A6 and A8-
A11 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bit A8 set to one, and bits A0-
A7 and A9-A11 set to the desired values. When a DLL Reset is complete the GDDR3 SDRAM reset bit 8 of the mode register to a zero.
After DLL Reset MRS, Power down can not be issued within 10 clock.
In case the clock frequency need to be changed after the power-up, 512Mb GDDR3 doesn’t require DLL reset. Instead, DLL should
be disabled first before the frequency changed and then change the clock frequency as needed. After the clock frequency changed,
there needed some time till clock become stable and then enable the DLL and then 20K cycle required to lock the DLL
Clock frequency change sequence after the power-up(example)
Command
Wait until
clock stable
CK,CK
700Mbps
1000Mbps
DEMRS
EMRS
DLL Enable
20K cycle for
DLL locking time
~
~
~
~
Any
Command
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4J52324QE-BC12000 制造商:Samsung Semiconductor 功能描述:
K4J52324QE-BC14000 制造商:Samsung Semiconductor 功能描述:
K4J52324QE-BC16000 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC - Trays
K4J52324QH-AC14000 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC LEAD PART 10W - Trays
K4J55323QF-GC 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR3 SDRAM
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