參數(shù)資料
型號： K4J52324QC-BJ12
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 512Mbit GDDR3 SDRAM
中文描述： 512MB的GDDR3 SDRAM的
文件頁數(shù)： 55/57頁
文件大?。?/td> 1246K
代理商： K4J52324QC-BJ12
- 55 -
Rev 1.0 (Mar 2005)
512M GDDR3 SDRAM
K4J52324QC-B
AC CHARACTERISTICS (I-II)
Note : 1. The WRITE latency can be set from 1 to 7 clocks. When the WRITE latency is set to 1 or 2 or 3 clocks, the input buffers are turned on during the
ACTIVE commands reducing the latency but added power. When the WRITE latency is set to 4 ~7 clocks which must be greater than 7ns, the
input buffers are turned on during the WRITE commands for lower power operation.
2. A low to high transition on the WDQS line is not allowed in the half clock prior to the write preamble.
3. The last rising edge of WDQS after the write postamble must be riven high by the controller. WDQS can not be pulled high by
the on-die termination alone.
4. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific
voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
5. The cycle to cycle jitter over 1~6 cycle short term jitter
Parameter
Sym-
bol
t
DQSCK
t
CH
t
CL
-BC14
-BC16
-BC20
Unit Note
Min
-0.26
0.45
0.45
Max
+0.26
0.55
0.55
Min
-0.29
0.45
0.45
-
Max
+0.29
0.55
0.55
Min
-0.35
0.45
0.45
-
Max
+0.35
0.55
0.55
DQS out access time from CK
CK high-level width
CK low-level width
ns
tCK
tCK
ns
ns
ns
ns
ns
tCK
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
tCK
CK cycle time
CL=11
CL=10
CL=9
CL=8
CL=7
t
CK
3.3
3.3
3.3
1.4
1.6
2.0
2.0
5
0.18
0.18
10
10
0.48
0.48
-0.160
0.4
0.4
1.6
2.0
2.0
5
0.20
0.20
10
10
0.48
0.48
0.180
0.4
0.4
-
-
2.0
4
0.25
0.25
10
10
0.48
0.48
0.225
0.4
0.4
WRITE Latency
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
Active termination setup time
Active termination hold time
DQS input high pulse width
DQS input low pulse widthl
Data strobe edge to Dout edge
DQS read preamble
DQS read postamble
Write command to first DQS latching transition
DQS write preamble
DQS write preamble setup time
DQS write postamble
t
WL
t
DH
t
DS
t
ATS
t
ATH
t
DQSH
t
DQSL
t
DQSQ
t
RPRE
t
RPST
t
DQSS
t
WPRE
t
WPRES
t
WPST
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
0.52
0.52
0.160
0.6
0.6
0.52
0.52
0.180
0.6
0.6
0.52
0.52
0.225
0.6
0.6
WL-0.2
0.4
0
0.4
tCLmin or
tCHmin
t
HP
-0.16
WL+0.2
0.6
-
0.6
WL-0.2
0.4
0
0.4
tCLmin or
tCHmin
t
HP
-0.18
WL+0.2
0.6
-
0.6
WL-0.2
0.4
0
0.4
tCLmin or
tCHmin
t
HP
-0.225
WL+0.2
0.6
-
0.6
2
3
Half strobe period
t
HP
-
-
-
tCK
Data output hold time from DQS
Data-out high-impedance window
from CK and /CK
Data-out low-impedance window from
CK and /CK
Address and control input hold time
Address and control input setup time
Address and control input pulse width
t
QH
-
-
-
ns
t
HZ
-0.3
-
-0.3
-
-0.3
-
ns
4
t
LZ
-0.3
-
-0.3
-
-0.3
-
ns
4
t
IH
t
IS
t
IPW
tJ
tDCERR
tR, tF
0.35
0.35
1.0
-
-
-
-
-
-
0.4
0.4
1.1
-
-
-
-
-
-
0.5
0.5
1.3
-
-
-
-
-
-
ns
ns
ns
tCK
tCK
tCK
Jitter over 1~6 clock cycle error
Cycle to cyde duty cycle error
Rise and fall times of CK
0.03
0.03
0.2
0.03
0.03
0.2
0.03
0.03
0.2
5
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