參數(shù)資料
型號： K4J52324QC-BJ12
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 512Mbit GDDR3 SDRAM
中文描述： 512MB的GDDR3 SDRAM的
文件頁數(shù)： 4/57頁
文件大?。?/td> 1246K
代理商： K4J52324QC-BJ12
- 4 -
Rev 1.0 (Mar 2005)
512M GDDR3 SDRAM
K4J52324QC-B
2M x 32Bit x 8 Banks Graphic Double Data Rate 3 Synchronous DRAM
with Uni-directional Data Strobe
2.0V + 0.1V power supply for device operation for -BJ**
2.0V + 0.1V power supply for I/O interface for -BJ**
1.8V + 0.1V power supply for device operation for -BC**
1.8V + 0.1V power supply for I/O interface for -BC**
On-Die Termination (ODT)
Output Driver Strength adjustment by EMRS
Calibrated output drive
1.8V Pseudo Open drain compatible inputs/outputs
4 internal banks for concurrent operation
Differential clock inputs (CK and CK)
Commands entered on each positive CK edge
CAS latency : 4, 5, 6, 7, 8, 9, 10, 11 (clock)
Additive latency (AL): 0 and 1 (clock)
Programmable Burst length : 4 and 8
Programmable Write latency : 1, 2, 3, 4, 5, 6 and 7 (clock)
GENERAL DESCRIPTION
FOR 2M x 32Bit x 8 Bank GDDR3 SDRAM
FEATURES
Single ended READ strobe (RDQS) per byte
Single ended WRITE strobe (WDQS) per byte
RDQS edge-aligned with data for READs
WDQS center-aligned with data for WRITEs
Data Mask(DM) for masking WRITE data
Auto & Self refresh modes
Auto Precharge option
32ms, auto refresh (8K cycle)
136 Ball FBGA
Maximum clock frequency up to 800MHz
Maximum data rate up to 1.6Gbps/pin
DLL for outputs
Boundary scan function with SEN pin
Mirror function with MF pin
ORDERING INFORMATION
Part NO.
* K4J52324QC-A*** is leaded package part number
Max Freq.
Max Data Rate
VDD&VDDQ
Package
K4J52324QC-BJ12
800MHz
1.6Gbps/pin
2.0V+0.1V
136 Ball FBGA
K4J52324QC-BJ14
700MHz
1.4Gbps/pin
K4J52324QC-BC14
700MHz
1.4Gbps/pin
1.8V+0.1V
K4J52324QC-BC16
600MHz
1.2Gbps/pin
K4J52324QC-BC20
500MHz
1.0Gbps/pin
The K4J52324QC is 536,870,912 bits of hyper synchronous data rate Dynamic RAM organized as 8 x 2,097,152 words by
32 bits, fabricated with SAMSUNG
’s
high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 6.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, and programmable latencies allow the device to be useful for a variety of high performance memory
system applications.
相關(guān)PDF資料
PDF描述
K4J52324QC-BJ14 512Mbit GDDR3 SDRAM
K4M281633F 2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA
K4M281633F-C 2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA
K4M281633F-F1L 2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA
K4M281633F-G 2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4J52324QC-BJ14 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM
K4J52324QE-BC12000 制造商:Samsung Semiconductor 功能描述:
K4J52324QE-BC14000 制造商:Samsung Semiconductor 功能描述:
K4J52324QE-BC16000 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC - Trays
K4J52324QH-AC14000 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC LEAD PART 10W - Trays
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