- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374275 > K4J52324QC-BC20 (SAMSUNG SEMICONDUCTOR CO. LTD.) 512Mbit GDDR3 SDRAM PDF資料下載
參數(shù)資料
| 型號： | K4J52324QC-BC20 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Mbit GDDR3 SDRAM |
| 中文描述： | 512MB的GDDR3 SDRAM的 |
| 文件頁數(shù)： | 44/57頁 |
| 文件大?。?/td> | 1246K |
| 代理商： | K4J52324QC-BC20 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當(dāng)前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁
- 44 -
Rev 1.0 (Mar 2005)
512M GDDR3 SDRAM
K4J52324QC-B
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a
particular bank or the open row in all banks. The bank(s) will be available
for a subsequent row access some specified time (t
RP
) after the PRE-
CHARGE command is issued. Input A8 determines whether one or all
banks are to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1, BA2 select the bank. When all banks
are to be precharged, inputs BA0, BA1, BA2 are treated as "Don’t Care."
Once a bank has been precharged, it is in the idle state and must be acti-
vated prior to any READ or WRITE commands being issued to the bank.
POWER-DOWN (CKE NOT ACTIVE)
Unlike SDR SDRAMs,GDDR3(x32) SDRAM requires CKE to be active
at all times an access is in progress; from the issuing of a READ or
WRITE command until completion of the burst. For READs, a burst com-
pletion is defined when the Read Postamble is satisfied; For WRITEs, a
burst completion is defined BL/2 cycles after the Write Postamble is sat-
isfied.
Power-down is entered when CKE is registered LOW. If power-down
occurs when there is a row active in any bank, this mode is referred to as
active power-down. Entering power-down deactivates the input and out-
put buffers, excluding CK,/CK and CKE. For maximum power savings,
the user has the option of disabling the DLL prior to entering power-
down. However, power-down duration is limited by the refresh require-
ments of the device, so in most applications,the self-refresh mode is pre-
ferred over the DLL-disabled power-down mode.
When in power-down, CKE LOW and a stable clock signal must be
maintained at the inputs of the GDDR3 SDRAM, while all other input sig-
nals are "Don’t Care" except data terminator disable command.
The power-down state is synchronously exited when CKE is registered
HIGH (in conjunction with a NOP or DESELECT command). A valid exe-
cutable command may be applied tPDEX later.
ALL BANKS
ONE BANK
BA
/CS
/RAS
/CAS
/WE
A0-A7, A9-A11
BA0,1,2
BA=Bank Address
(if A8 is LOW; otherwise "Don’t Care")
/CK
CK
CKE
HIGH
A8
DON’T CARE
PRECHARGE Command
NOP
NOP
NOP
VALID
T0
T1
Ta0
Ta1
Ta2
/CK
CK
COMMAND
VALID
Ta7
T2
CKE
t
IS
t
PDEX
t
IS
No PEAD/WRITE
access in progress
* Enter power - down mode
Exit power - down mode
Power-Down
* Once the device enters the power down mode, it should be in NOP state at least for 10ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4J52324QC-BJ12 | 512Mbit GDDR3 SDRAM |
| K4J52324QC-BJ14 | 512Mbit GDDR3 SDRAM |
| K4M281633F | 2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
| K4M281633F-C | 2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
| K4M281633F-F1L | 2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4J52324QC-BJ12 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-BJ14 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QE-BC12000 | 制造商:Samsung Semiconductor 功能描述: |
| K4J52324QE-BC14000 | 制造商:Samsung Semiconductor 功能描述: |
| K4J52324QE-BC16000 | 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。