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參數(shù)資料
| 型號： | K4J52324QC-BC20 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Mbit GDDR3 SDRAM |
| 中文描述： | 512MB的GDDR3 SDRAM的 |
| 文件頁數(shù)： | 20/57頁 |
| 文件大?。?/td> | 1246K |
| 代理商： | K4J52324QC-BC20 |
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- 20 -
Rev 1.0 (Mar 2005)
512M GDDR3 SDRAM
K4J52324QC-B
BOUNDARY SCAN FUNCTION
Figure 1. Internal Block Diagram (Reference Only)
Pins under test
CK
D
DQ
DM0
Tie to Iogic 0
CK
D
DQ
DQS
CK
D
DQ
DQ4
CK
D
DQ
RDQS0
RES (SSH,Scan Shift)
CS# (SCK, Scan Clock)
MF (SOE#, Output Enable)
RFU at V-4 (SEN, Scan Enable)
WDQS0 (SOUT,Scan Out)
Puts device into scan mode and re-maps pins to scan functionality
Dedicated Scan Flops
(1per signal under test)
The following lists the rest of the signals on the scan chain:
DQ[3:0], DQ[31:6], RDQS[3:1], WDQS[3:1], DM[3:1], RFU,
CAS#, WE#, CKE, BA[2:0], A[11:0], CK, CK# and ZQ
Two RFU’s(I-2 and J-3 on 136-ball package) will be on the
scan chain and will read as a logic "0"
The following lists signals not on the scan chain:
NC, VDD, VSS, VDDQ, VSSQ, VREF
In case ZQ pin is connected to the external resistor, it will
be read as logic "0". However, if the ZQ pin is open, it will
be read as floating. Accordingly, ZQ pin should be driven
by any signal.
GENERAL INFORMATION
The 512Mb GDDR3 incorporates a modified boundary scan test mode as an optional feature. This mode doesn’t operate in accor-
dance with IEEE Standard 1149.1 - 1990. To save the current GDDR3 ball-out, this mode will scan parallel data input and output and
the scanned data through WDQS0 pin controlled by an add-on pin, SEN which is located at V-4 of 136 ball package.
For the normal device operation other than boundary scan, there required device re-initialization by device power-off and then power-on.
DISABLING THE SCAN FEATURE
It is possible to operate the 512Mb GDDR3 without using the boundary scan feature. SEN(at V-4 of 136 ball package) should be tied
LOW(VSS) to prevent the device from entering the boundary scan mode. The other pins which are used for scan mode, RES, MF,
WDQS0 and CS# will be operating at normal GDDR3 functionalities when SEN is deasserted.
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| K4J52324QC-BJ12 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-BJ14 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
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