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參數(shù)資料
| 型號： | K4J52324QC-BC14 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Mbit GDDR3 SDRAM |
| 中文描述： | 512MB的GDDR3 SDRAM的 |
| 文件頁數(shù)： | 50/57頁 |
| 文件大?。?/td> | 1246K |
| 代理商： | K4J52324QC-BC14 |
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- 50 -
Rev 1.0 (Mar 2005)
512M GDDR3 SDRAM
K4J52324QC-B
3. Current state definitions :
Idle : The bank has been precharged, and t
RP
has been met.
Row Active : A row in the bank has been activated, and t
RCD
has been met.
No data bursts/accesses and no register accesses are in progress.
Read : A READ burst has been initiated, with auto precharge disabled.
Write : A WRITE burst has been initiated, with auto precharge disabled.
Read w/ Auto- Precharge Enabled : See following text
Write w/ Auto- Precharge Enabled : See following text
3a. The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two
parts : the access period and the precharge period. For read with auto precharge, the precharge period is defined
as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRE-
CHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge
period begins when tWR ends, with tWR command and ends where the precharge period (or t
RP
) begins.
During the precharge period of the read with auto precharge enabled or write with auto precharge enabled states,
ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied. In either case, all other
related Limitations apply (e.g., contention between read data write data must be avoided).
3b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different
bank is summarized below.
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. All states and sequences not shown are illegal or reserved.
6. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
7. Requires appropriate DM masking.
From Command
To Command
Minimum delay (with concurrent auto precharge)
WRITE w/AP
READ or READ w/AP
[WL + (BL/2)] tCK + tWR
WRITE or WRITE w/AP
(BL/2) * tCK
PRECHARGE
1 tCK
ACTIVE
1 tCK
READ w/AP
READ or READ w/AP
(BL/2) * tCK
WRITE or WRITE w/AP
[CL
RU
+ (BL/2)] + 1 - WL * tCK
PRECHARGE
1 tCK
ACTIVE
1 tCK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4J52324QC-BC14000 | 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC LEAD PART 10W - Trays |
| K4J52324QC-BC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-BC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-BJ12 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-BJ14 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
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