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參數(shù)資料
| 型號： | K4J52324QC-BC14 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Mbit GDDR3 SDRAM |
| 中文描述： | 512MB的GDDR3 SDRAM的 |
| 文件頁數(shù)： | 27/57頁 |
| 文件大?。?/td> | 1246K |
| 代理商： | K4J52324QC-BC14 |
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- 27 -
Rev 1.0 (Mar 2005)
512M GDDR3 SDRAM
K4J52324QC-B
ON-DIE TERMINATION
Bus snooping for READ commands other than /CS is used to control the on-die termination in the dual load configuration.
The GDDR3 SDRAM will disable the on-die termination when a READ command is detected, regardless of the state of
/CS, when the ODT for the DQ pins are set for dual loads (120
).
The on-die termination is disabled x clocks after the
READ command where x equals CL-1 and stay off for a duration of BL/2 + 2, as below figure, Data Termination Disable
Timing. In a two-rank system, both DRAM devices snoop the bus for READ commands to either device and both will dis-
able the on-die termination if a READ command is detected. The on-die termination for all other pins on the device are
always on for both a single-rank system and a dual-rank system.
The on-die termination value on address and control pins is determined during power-up in relation to the state of CKE on
the first transition of RESET. On the rising edge of RESET, if CKE is sampled LOW, then the configuration is determined to
be a single-rank system. The on-die termination is then set to one-half ZQ for the address pins. On the rising edge of
RESET, if CKE is sampled HIGH, then the configuration is determined to be a dual-rank system. The on-die termination for
the DQs, WDQS, and DM pins is set in the EMRS.
NOP
NOP
NOP
NOP
NOP
READ
T0
T7
T8
T8n
T9
T9n
T10
T11
CK#
CK
COMMAND
ADDRESS
RDQS
DQ
～
～
～
～
～
～
～
～
Bank a,
Col n
CL = 8
DO
n
DQ
TERMINATION
GDDR3 Data Termination is Disabled
Data Termination Disable Timing
Note :
1. DO
n
= data-out from column
n
.
2. Burst length = 4.
3. Three subsequent elements of data-out appear in the specified order following DO
n
.
4. Shown with nominal t
AC
and t
DQSQ
.
5. RDQS will start driving high one-half cycle prior to the first falling edge.
6. The Data Terminators are disabled starting at CL-1 and the duration is BL/2 + 2
7. READS to either rank disable both ranks’ termination regardless of the logic level of /CS.
DON’T CARE
TRANSITIONING DATA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4J52324QC-BC14000 | 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC LEAD PART 10W - Trays |
| K4J52324QC-BC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-BC20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-BJ12 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-BJ14 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
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