參數(shù)資料
型號(hào)： K4J52324QC-BC14
廠(chǎng)商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 512Mbit GDDR3 SDRAM
中文描述： 512MB的GDDR3 SDRAM的
文件頁(yè)數(shù)： 10/57頁(yè)
文件大?。?/td> 1246K
代理商： K4J52324QC-BC14
- 10 -
Rev 1.0 (Mar 2005)
512M GDDR3 SDRAM
K4J52324QC-B
INITIALIZATION
GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than
those
specified may result in undefined operation.
1. Apply power and keep CKE/RESET at low state ( All other inputs may be undefined)
- Apply VDD and VDDQ simultaneously
- Apply VDDQ before Vref. ( Inputs are not recognized as valid until after V
REF
is applied )
2. Required minimum 100us for the stable power before RESET pin transition to HIGH
- Upon power-up the address/command active termination value will automatically be set based off the state of RESET and CKE.
- On the rising edge of RESET the CKE pin is latched to determine the address and command bus termination value.
If CKE is sampled at a zero the address termination is set to 1/2 of ZQ.
If CKE is sampled at a one the address termination is set to ZQ.
- RESET must be maintained at a logic LOW level and CS at a logic high value during power-up to ensure that the DQ outputs will
be in a High-Z state, all active terminators off, and all DLLs off.
4. Minimum 200us delay required prior to applying any executable command after stable power and clock.
5. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, then RESET and CKE should be
brought to HIGH,
6. Issue a PRECHARGE ALL command following after NOP command.
7. Issue a EMRS command (BA1BA0="01") to enable the DLL.
8. Issue MRS command (BA0BA1 = "00") to reset the DLL and to program the operating parameters.
20K clock cycles are required between the DLL to lock.
9. Issue a PRECHARGE ALL command
10 . Issue at least two AUTO refresh command to update the driver impedance and calibrate the output drivers.
Following these requirements, the GDDR3 SDRAM is ready for normal operation.
CODE
V
DD
V
DDQ
V
REF
CK
CK
RES
CKE
CKE
COMMAND
DM
A0-A7, A9-A11
A8
BA0, BA1
RDQS
WDQS
DQ
RA
CODE
RA
CODE
BAO=H,
BA
NOP
PRE
LMR
LMR
PRE
AR
AR
ACT
High
High
High
BAO=L,
T=10ns
Po and
V
CK stable
T = 200us
tRP
tMRD
tRFC
tRP
tRFC
Load Extended
Mode Register
tMRD
20K
Load Mode
Register
DLL Reset
t
IS
t
IH
CODE
t
IS
t
IH
t
IS
t
IH
t
IS
t
IH
t
IS
t
IH
t
IS
t
IH
T0
T1
Ta0
Tb0
Tc0
Td0
Te0
Tf0
t
ATS
t
ATH
t
CH
t
CL
t
IS
t
IH
Precharge
All Banks
Precharge
All Banks
1st
Auto Refresh
2nd
Auto Refresh
ALL BANKS
ALL BANKS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4J52324QC-BC14000 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC LEAD PART 10W - Trays
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