參數(shù)資料
型號: K4H561638C-TCB0
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
元件分類: 串行ADC
英文描述: 10-Bit, 38 kSPS ADC Serial Out, On-Chip System Clock, 11 Ch. 20-SOIC
中文描述: 128MB DDR SDRAM的
文件頁數(shù): 11/18頁
文件大?。?/td> 168K
代理商: K4H561638C-TCB0
DDR SDRAM
DDR SDRAM 256Mb D-die (x8, x16)
Rev. 1.1 Feb. 2003
DDR SDRAM I
DD
spec table
(V
DD
=2.7V, T = 10
°
C)
Symbol
32Mx8
16Mx16
Unit
Notes
- CC(DDR400@CL=3) - C4(DDR400@CL=3) - CC(DDR400@CL=3) - C4(DDR400@CL=3)
105
100
130
130
4
4
30
30
25
25
55
55
75
75
185
185
220
220
200
200
3
3
1.5
1.5
350
350
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
110
150
4
30
25
55
75
220
250
200
3
1.5
380
105
145
4
30
25
55
75
220
250
200
3
1.5
380
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD6
Normal
Low power
IDD7A
Optional
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs change logic state once per Deselect cycle.
Iout = 0mA
2. Timing patterns
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N N R0 N N N N P0 N N
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
IDD7A : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on Deselet edge are not changing.
Iout = 1mA
2. Timing patterns
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A = Activate, R=Read, W=Write, P=Precharge, N=NOP
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