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參數資料
| 型號： | K4H560438D-GC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR 256Mb |
| 中文描述： | 的DDR 256Mb的 |
| 文件頁數： | 19/26頁 |
| 文件大小： | 291K |
| 代理商： | K4H560438D-GC |
- 19 -
K4H560838D
DDR SDRAM
Rev. 2.2 Mar. ’03
8. I/O Setup/Hold Plateau Derating
I/O Input Level
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF
±
310mV for a duration of
up to 2ns.
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
tDS
tDH
(ns/V)
(ps)
(ps)
This derating table is used to increase t
DS
/t
DH
in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
tDS
tDH
(mV)
±
280
(ps)
+50
(ps)
+50
Delta Rise/Fall Rate
0
0
0
±
0.25
±
0.5
+50
+50
+100
+100
The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.
tIH/tIS
(ps)
(ps)
1.0V/ns
0
0
CK slew rate
(Single ended)
tDSS/tDSH
tAC/tDQSCK
(ps)
0
tLZ(min)
(ps)
0
tHZ(max)
(ps)
0
0.75V/ns
0.5V/ns
+50
+100
+50
+100
+50
+100
-50
-100
+50
+100
<Reference>
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