- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374272 > K4H510838C-TCA2 (SAMSUNG SEMICONDUCTOR CO. LTD.) 8-Bit, 392 kSPS ADC Parallel Out, Microprocessor Peripheral, On-Chip Track-and-Hold, Single Channels 20-PDIP PDF資料下載
參數(shù)資料
| 型號： | K4H510838C-TCA2 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | ADC |
| 英文描述： | 8-Bit, 392 kSPS ADC Parallel Out, Microprocessor Peripheral, On-Chip Track-and-Hold, Single Channels 20-PDIP |
| 中文描述： | 128MB DDR SDRAM的 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 366K |
| 代理商： | K4H510838C-TCA2 |
Rev. 0.3 June. 2005
DDR SDRAM
DDR SDRAM 512Mb D-die (x8, x16)
Preliminary
The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure proper system
performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 :
Input Slew Rate for DQ, DQS, and DM
Table 2
:
Input Setup & Hold Time Derating for Slew Rate
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS
DDR333
DDR266
DDR200
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
Units
Notes
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
DCSLEW
TBD
TBD
TBD
TBD
0.5
4.0
V/ns
a, m
Input Slew Rate
tIS
tIH
Units
Notes
0.5 V/ns
0
0
ps
i
0.4 V/ns
+50
0
ps
i
0.3 V/ns
+100
0
ps
i
Input Slew Rate
tDS
tDH
Units
Notes
0.5 V/ns
0
0
ps
k
0.4 V/ns
+75
+75
ps
k
0.3 V/ns
+150
+150
ps
k
Delta Slew Rate
tDS
tDH
Units
Notes
+/- 0.0 V/ns
0
0
ps
j
+/- 0.25 V/ns
+50
+50
ps
j
+/- 0.5 V/ns
+100
+100
ps
j
Slew Rate Characteristic
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Notes
Pullup Slew Rate
1.2 ~ 2.5
1.0
4.5
a,c,d,f,g,h
Pulldown slew
1.2 ~ 2.5
1.0
4.5
b,c,d,f,g,h
Slew Rate Characteristic
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Notes
Pullup Slew Rate
1.2 ~ 2.5
0.7
5.0
a,c,d,f,g,h
Pulldown slew
1.2 ~ 2.5
0.7
5.0
b,c,d,f,g,h
AC CHARACTERISTICS
DDR266B
DDR200
PARAMETER
MIN
MAX
MIN
MAX
Notes
Output Slew Rate Matching Ratio (Pullup to Pulldown)
TBD
TBD
0.67
1.5
e,m
20.0 System Characteristics for DDR SDRAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4H510838C-TCB0 | 8-Bit, 392 kSPS ADC Parallel Out, Microprocessor Peripheral, On-Chip Track-and-Hold, Single Channels 20-SOIC |
| K4H510838C-TLA0 | 8-Bit, 392 kSPS ADC Parallel Out, Microprocessor Peripheral, On-Chip Track-and-Hold, Single Channels 20-SOIC |
| K4H510838C-TLA2 | 8-Bit, 392 kSPS ADC Parallel Out, Microprocessor Peripheral, On-Chip Track-and-Hold, Single Channels 20-SOIC |
| K4H510838C-TLB0 | 8-Bit, 392 kSPS ADC Parallel Out, Microprocessor Peripheral, On-Chip Track-and-Hold, Single Channels 20-SOIC |
| K4H510838C-UCB0 | 8-Bit, 392 kSPS ADC Parallel Out, Microprocessor Peripheral, On-Chip Track-and-Hold, Single Channels 20-PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4H510838C-TCB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H510838C-TLA0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H510838C-TLA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H510838C-TLB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H510838C-UC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb C-die DDR SDRAM Specification |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。