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REV. 1.0 November. 2. 2000
128Mb DDR SDRAM
3.3.10 DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read
cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the
corresponding data.(DM to data-mask latency is zero).
DM must be issued at the rising or falling edge of data strobe.
Command
< Burst Length=8 >
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQ
′
s
Din 0
Din 1
Din 2
Din 3
t
DQSS
DM
Din 4
Din 5
Din 6
Din7
masked by DM=H
2
0
1
5
3
4
8
6
7
CK
CK
6. When terminating a burst Read command, the BST command must be issued L
BST
(“BST Latency”) clock
cycles before the clock edge at which the output buffers are tristated, where L
BST
equals the CAS latency
for read operations. This is shown in previous page Figure with examples for CAS latency (CL) of 1.5, 2,
2.5, 3 and 3.5 (only selected CAS latencies are required by the DDR SDRAM standards, the others are
optional).
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s).
Figure 18. DM masking timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4H1G1638A-TCB0 | 128Mb DDR SDRAM |
| K4H1G1638A-TLA0 | RES FILM SMT 1.30 KOHM 0.062W 1.00% 250 |
| K4H1G1638A-TLA2 | 128Mb DDR SDRAM |
| K4H1G1638A-TLB0 | 128Mb DDR SDRAM |
| K4H1G1638B-TCA0 | 128Mb DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4H1G1638A-TCB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H1G1638A-TLA0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H1G1638A-TLA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H1G1638A-TLB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H1G1638B-TCA0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
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