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參數(shù)資料
| 型號： | K4D26323RA-GC2A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| 中文描述： | 100萬x 32Bit的× 4銀行雙數(shù)據(jù)速率同步RAM的雙向數(shù)據(jù)選通和DLL |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 315K |
| 代理商： | K4D26323RA-GC2A |
128M GDDR SDRAM
K4D26323QG-GC
- 12 -
Rev 1.2(Mar. 2005)
R
T
=50
Output
C
LOAD
=30pF
(Fig. 1) Output Load Circuit
Z0=50
V
REF
=0.5*V
DDQ
V
tt
=0.5*V
DDQ
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
Decoupling Capacitance between V
DD
and V
SS
C
DC1
0.1 + 0.01
uF
Decoupling Capacitance between V
DDQ
and V
SSQ
C
DC2
0.1 + 0.01
uF
1. V
DD
and V
DDQ
pins are separated each other.
All V
DD
pins are connected in chip. All V
DDQ
pins are connected in chip.
2. V
SS
and V
SSQ
pins are separated each other
All V
SS
pins are connected in chip. All V
SSQ
pins are connected in chip.
Note :
AC OPERATING TEST CONDITIONS
(T
A
= 0 to 65
°
C)
Note 1 : In case of differential clocks(CK and CK ), input reference voltage for clock is a CK and CK’s crossing point.
Parameter
Value
Unit
Note
Input reference voltage for CK(for single ended)
0.50*V
DDQ
V
1
CK and CK signal maximum peak swing
1.5
V
CK signal minimum slew rate
1.0
V/ns
Input Levels(V
IH
/V
IL
)
V
REF
+0.4/V
REF
-0.4
V
Input timing measurement reference level
V
REF
V
Output timing measurement reference level
V
tt
V
Output load condition
See Fig.1
CAPACITANCE
(T
A
= 25
°
C,
f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance(
CK, CK )
C
IN1
1.0
5.0
pF
Input capacitance(A
0
~A
11
, BA
0
~BA
1
)
C
IN2
1.0
4.0
pF
Input capacitance
(
CKE, CS, RAS,CAS, WE )
C
IN3
1.0
4.0
pF
Data & DQS input/output capacitance(DQ
0
~DQ
31
)
C
OUT
1.0
6.5
pF
Input capacitance(DM0 ~ DM3)
C
IN4
1.0
6.5
pF
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