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參數(shù)資料
| 型號： | K4D263238G-VC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mbit GDDR SDRAM |
| 中文描述： | 128Mbit GDDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 430K |
| 代理商： | K4D263238G-VC |
128M GDDR SDRAM
K4D263238G-GC
- 17 -
Rev 1.8 (March. 2005)
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL4, BL2)
1
tHP
CK, CK
DQS
DQ
CS
2
5
0
COMMAND
READA
tQH
Qa0
tDQSQ(max)
tDQSQ(max)
3
4
Qa1
VALID
NOP
NOP
NOP
NOP
NOP
NOP
VALID
t
IS
t
IS
CK, CK
CKE
Command
Exit Powr Down mode
Enter Power Down mode
(Read or Write operation
must not be in progress)
3t
CK
Power Down Timing
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| K4D263238M-QC60 | DIODE ZENER DUAL COMMON-CATHODE 300mW 3.3Vz 5mA-Izt 0.0606 0.1uA-Ir SOT-23 3K/REEL |
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| K4D263238M-QC45 | DIODE ZENER DUAL COMMON-CATHODE 300mW 39Vz 5mA-Izt 0.0513 0.1uA-Ir 29 SOT-23 3K/REEL |
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相關(guān)代理商/技術(shù)參數(shù) |
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| K4D263238I-GC50T00 | 制造商:Samsung 功能描述:DDR SGRAM X32 FBGA - Tape and Reel |
| K4D263238I-UC50 | 制造商:Samsung Semiconductor 功能描述: |
| K4D263238I-UC50T00 | 制造商:Samsung SDI 功能描述: |
| K4D263238I-VC40000 | 制造商:Samsung 功能描述:DDR SGRAM X32 FBGA - Trays |
| K4D263238I-VC50000 | 制造商:Samsung 功能描述:DDR SGRAM X32 FBGA - Trays |
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