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參數(shù)資料
| 型號： | K4D263238E-GC36 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DIODE ZENER TRIPLE ISOLATED 200mW 16.1Vz 10mA-Izt 0.02547 0.05uA-Ir 12 SOT-363 3K/REEL |
| 中文描述： | 100萬x 32Bit的× 4銀行圖形雙數(shù)據(jù)速率同步DRAM的雙向數(shù)據(jù)選通和DLL |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 310K |
| 代理商： | K4D263238E-GC36 |
128M GDDR SDRAM
K4D263238E-GC
- 5 -
Rev 1.7 (Nov. 2003)
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF
to CK pin.
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ
’
s and DM
’
s that are sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS
Input
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
WE
Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQS
0
~ DQS
3
Input/Output
Data input and output are synchronized with both edge of DQS.
DQS
0
for DQ
0
~ DQ
7,
DQS
1
for DQ
8
~ DQ
15,
DQS
2
for DQ
16
~ DQ
23,
DQS
3
for DQ
24
~ DQ
31.
DM
0
~ DM
3
Input
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM
0
for DQ
0
~ DQ
7,
DM
1
for DQ
8
~ DQ
15,
DM
2
for
DQ
16
~ DQ
23,
DM
3
for DQ
24
~ DQ
31.
DQ
0
~ DQ
31
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA
0
, BA
1
Input
Selects which bank is to be active.
A
0
~ A
11
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
0
~ RA
11
, Column addresses : CA
0
~ CA
7
.
Column address CA
8
is used for auto precharge.
V
DD
/V
SS
Power Supply
Power and ground for the input buffers and core logic.
V
DDQ
/V
SSQ
Power Supply
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
V
REF
Power Supply
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
Reserved for future use
This pin is recommended to be left "No connection" on the device
MCL
Must Connect Low
Must connect low
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4D263238E-GC40 | DIODE ZENER SINGLE 300mW 17.9Vz 10mA-Izt 0.02545 0.05uA-Ir 14 SOT-23 3K/REEL |
| K4D263238E-GC45 | DIODE ZENER TRIPLE ISOLATED 200mW 17.88Vz 10mA-Izt 0.02545 0.05uA-Ir 14 SOT-363 3K/REEL |
| K4D263238G-GC | 128Mbit GDDR SDRAM |
| K4D263238G-GC2A | 128Mbit GDDR SDRAM |
| K4D263238G-GC33 | 128Mbit GDDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4D263238E-GC40 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL |
| K4D263238E-GC45 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL |
| K4D263238F | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL |
| K4D263238F-QC40 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL |
| K4D263238F-QC50 | 制造商:Samsung Electro-Mechanics 功能描述:4M X 32 DDR DRAM, 0.7 ns, PQFP100 |
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