參數(shù)資料
型號: K4D263238A-GC33
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: DIODE ZENER SINGLE 500mW 2.7Vz 0.05mA-Izt 0.05 1uA-Ir 1 SOD-123 3K/REEL
中文描述: 100萬x 32Bit的× 4銀行雙數(shù)據(jù)速率同步DRAM的雙向數(shù)據(jù)選通和DLL
文件頁數(shù): 7/17頁
文件大?。?/td> 298K
代理商: K4D263238A-GC33
128M DDR SDRAM
K4D263238A-GC
- 7 -
Rev. 2.0 (Jan. 2003)
Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1
6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*
1,2
7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
FUNCTIONAL DESCRIPTION
Power up & Initialization Sequence
Command
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tRP
2 Clock min.
precharge
ALL Banks
2nd Auto
Refresh
Mode
Register Set
CoAny
t
RFC
~
1st Auto
Refresh
t
RFC
~
EMRS
MRS
2 Clock min.
DLL Reset
~
~
precharge
ALL Banks
t
RP
Inputs must be
stable for 200us
~
200 Clock min.
~
2 Clock min.
CK,CK
* When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
相關(guān)PDF資料
PDF描述
K4D263238A-GC36 DIODE ZENER SINGLE 500mW 3Vz 0.05mA-Izt 0.05 0.8uA-Ir 1 SOD-123 3K/REEL
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