參數(shù)資料
型號(hào)： K4D261638F-TC25
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 128Mbit GDDR SDRAM
中文描述： 128Mbit GDDR SDRAM內(nèi)存
文件頁(yè)數(shù)： 14/18頁(yè)
文件大?。?/td> 225K
代理商： K4D261638F-TC25
128M GDDR SDRAM
K4D261638F
- 14 -
Rev. 1.2 (Jan. 2004)
AC CHARACTERISTICS - 2
Parameter
Symbol
-36
-40
-50
Unit
Note
Min
-
3.6
-
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.40
0.40
tCLmin
or
tCHmin
tHP-0.4
Max
Min
4.0
-
-
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
tHP-0.4
Max
Min
5.0
-
-
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.8
0
0.3
0.4
0.4
0.4
1.0
1.0
0.45
0.45
tCLmin
or
tCHmin
tHP-0.45
Max
CK cycle time
CL=3
CL=4
CL=5
t
CK
10
10
10
ns
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
t
CH
t
CL
t
DQSCK
t
AC
t
DQSQ
t
RPRE
t
RPST
t
DQSS
t
WPRES
t
WPREH
t
WPST
t
DQSH
t
DQSL
t
IS
t
IH
t
DS
t
DH
0.55
0.55
0.6
0.6
0.40
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
0.55
0.55
0.7
0.7
0.45
1.1
0.6
1.2
-
-
0.6
0.6
0.6
-
-
-
-
1
Clock half period
t
HP
-
-
-
ns
1
Data output hold time from DQS
t
QH
-
-
-
ns
1
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst
case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
相關(guān)PDF資料
PDF描述
K4D261638F-TC2A 128Mbit GDDR SDRAM
K4D261638F-TC33 128Mbit GDDR SDRAM
K4D261638F-TC36 128Mbit GDDR SDRAM
K4D261638F-TC40 128Mbit GDDR SDRAM
K4D261638F-TC50 128Mbit GDDR SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4D261638F-TC2A 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit GDDR SDRAM
K4D261638F-TC33 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit GDDR SDRAM
K4D261638F-TC36 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit GDDR SDRAM
K4D261638F-TC40 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit GDDR SDRAM
K4D261638F-TC50 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit GDDR SDRAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*