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參數(shù)資料
| 型號(hào)： | K4B1G1646C-ZCG9 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Gb C-die DDR3 SDRAM Specification |
| 中文描述： | 1Gb的?芯片的DDR3 SDRAM規(guī)范 |
| 文件頁數(shù)： | 50/63頁 |
| 文件大?。?/td> | 1255K |
| 代理商： | K4B1G1646C-ZCG9 |
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Page 50 of 63
Rev. 1.0 June 2007
1Gb DDR3 SDRAM
K4B1G04(08/16)46C
[ Table 51 ] Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
Units
Note
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
Power Down Timing
Exit Power Down with DLL on to any valid command;Exit
Percharge Power Down with DLL
frozen to commands not requiring a locked DLL
t
XP
max
(3t
CK
,7.5ns)
-
max
(3t
CK
,7.5ns)
-
max
(3t
CK
,6ns)
-
Exit Precharge Power Down with DLL frozen to commands
requiring a locked DLL
t
XPDLL
max
(10t
CK
,24ns)
-
max
(10t
CK
,24ns)
-
max
(10t
CK
,24ns)
-
2
CKE minimum pulse width
t
CKE
max
(3t
CK
,7.5ns)
-
max
(3t
CK
,5.625ns)
-
max
(3t
CK
,5.625ns)
-
Command pass disable delay
t
CPDED
1
-
1
-
1
-
nCK
Power Down Entry to Exit Timing
t
PD
t
CKE
(min)
9*t
REFI
t
CKE
(min)
9*t
REFI
t
CKE
(min)
9*t
REFI
t
CK
15
Timing of ACT command to Power Down entry
t
ACTPDEN
1
-
1
-
1
-
nCK
20
Timing of PRE command to Power Down entry
t
PRPDEN
1
-
1
-
1
-
nCK
20
Timing of RD/RDA command to Power Down entry
t
RDPDEN
RL + 4 +1
-
RL + 4 +1
-
RL + 4 +1
-
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
t
WRPDEN
WL + 4 +(t
WR
/
t
CK
)
-
WL + 4 +(t
WR
/
t
CK
)
-
WL + 4 +(t
WR
/
t
CK
)
-
nCK
9
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
t
WRAPDEN
WL + 4 +WR +1
-
WL + 4 +WR +1
-
WL + 4 +WR +1
-
nCK
10
Timing of WR command to Power Down entry
(BL4MRS)
t
WRPDEN
WL + 2 +(t
WR
/
t
CK
)
-
WL + 2 +(t
WR
/
t
CK
)
-
WL + 2 +(t
WR
/
t
CK
)
-
nCK
9
Timing of WRA command to Power Down entry
(BL4MRS)
t
WRAPDEN
WL +2 +WR +1
-
WL +2 +WR +1
-
WL +2 +WR +1
-
nCK
10
Timing of REF command to Power Down entry
t
REFPDEN
1
-
1
-
1
-
20,21
Timing of MRS command to Power Down entry
t
MRSPDEN
t
MOD(min)
-
t
MOD(min)
-
t
MOD(min)
-
t
CK
ODT Timing
ODT high time without write command or with wirte com-
mand and BC4
ODTH4
4
-
4
-
4
-
nCK
ODT high time with Write command and BL8
ODTH8
6
-
6
-
6
-
nCK
Asynchronous RTT tum-on delay (Power-Down with DLL
frozen)
t
AONPD
1
9
1
9
1
9
ns
Asynchronous RTT tum-off delay (Power-Down with DLL
frozen)
t
AOFPD
1
9
1
9
1
9
ns
ODT turn-on
t
AON
-400
400
-300
30
-250
250
ps
7,12
RTT_NOM and RTT_WR turn-off time from ODTLoff refer-
ence
t
AOF
0.3
0.7
0.3
0.7
0.3
0.7
t
CK(avg)
8,12
RTT dynamic change skew
t
ADC
0.3
0.7
0.3
0.7
0.3
0.7
t
CK(avg)
12
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining mode is
programmed
t
WLMRD
40
-
40
-
40
-
t
CK
3
DQS/DQS delay after tDQS margining mode is programmed
t
WLDQSEN
25
-
25
-
25
-
t
CK
3
Setup time for tDQSS latch
t
WLS
325
-
245
-
195
-
ps
Hold time of tDQSS latch
t
WLH
325
-
245
-
195
-
ps
Write leveling output delay
t
WLO
0
9
0
9
0
9
ns
Write leveling output error
t
WLOE
0
2
0
2
0
2
ns
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