參數(shù)資料
型號： K4B1G1646C-ZCF7
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 1Gb C-die DDR3 SDRAM Specification
中文描述： 1Gb的?芯片的DDR3 SDRAM規(guī)范
文件頁數(shù)： 45/63頁
文件大?。?/td> 1255K
代理商： K4B1G1646C-ZCF7
Page 45 of 63
Rev. 1.0 June 2007
1Gb DDR3 SDRAM
K4B1G04(08/16)46C
[ Table 46 ] Clock Jitter specification
Note : The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the
DDR3 SDRAM device.
Add note for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses:
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses:
∑ ∑
j=1
Add note for tJIT(duty)
tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH form tCH(avg). tCL jitter is the
largest deviation of any single tCL from tCL(avg)
tJIT(duty) = min/max of {tJIT(CH), tJIT(CL)}, where:
tJIT(CH) = {tCHi-tCH(avg) where i=1 to 200}, tJIT(CL) = {tCLi-tCL(avg) where i=1 to 200},
Add note for tJIT(per), tJIT(per,lck)
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200}
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing
Add note for tJIT(cc), tJIT(cc,lck)
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of {tCKi+1-tCKi}
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing
Add note for tERR(nper)
tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). This definition is TBD.
Parameter
Symbol
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
min
max
min
max
min
max
min
max
Clock period jitter
tJIT(per)
-100
100
-90
90
-80
80
-70
70
ps
Clock period jitter during DLL lock-
ing period
tJIT(per,lck)
-90
90
-80
80
-70
70
-60
60
ps
Cycle to cycle clock period jitter
tJIT(cc)
200
180
160
140
ps
Cycle to cycle clock period jitter
during DLL locking period
tJIT(cc,lck)
180
160
140
120
ps
Cumulative error across n cycles
tERR(nper)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
Average high pulse width
tCH(avg)
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Duty cycle jitter
tJIT(duty)
-100
100
-75
75
-60
60
-50
50
ps
tCHj
N x tCK(avg)
N=200
j=1
tCLj
N x tCK(avg)
12.2 Clock Jitter Specification
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參數(shù)描述
K4B1G1646C-ZCG9 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb C-die DDR3 SDRAM Specification
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