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| 型號： | K4B1G1646C-ZCF7 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Gb C-die DDR3 SDRAM Specification |
| 中文描述： | 1Gb的?芯片的DDR3 SDRAM規(guī)范 |
| 文件頁數(shù)： | 35/63頁 |
| 文件大?。?/td> | 1255K |
| 代理商： | K4B1G1646C-ZCF7 |
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Page 35 of 63
Rev. 1.0 June 2007
1Gb DDR3 SDRAM
K4B1G04(08/16)46C
[ Table 35 ] IDD Measurement Conditions for IDD2N, IDD2P(1), IDD2P(0) and IDD2Q
Note :
1. In DDR3 the MRS Bit 12 defines DLL on/off behavior ONLY for precharge power down. There are 2 different Precharge Power Down states possible
: one with DLL on (fast exit, bit 12 = 1) and one with DLL off (slow exit, bit 12 = 0).
2. Because it is an exit after precharge power down the valid commands are: Activate, Refresh, Mode-Register Set, Enter - Self Refresh.
Current
IDD2N
IDD2P(1) a
IDD2P(0)
IDD2Q
Name
Precharge
Standby Current
Precharge Power
Down Current
Fast Exit -
MRS A12 Bit = 1
Precharge Power
Down Current
Slow Exit -
MRS A12 Bit = 0
Precharge Quiet
Standby Current
Measurement Condition
Timing Diagram Example
Figure 2
CKE
HIGH
LOW
LOW
LOW
External Clock
on
on
on
on
t
CK
t
CKmin
(IDD)
t
CKmin
(IDD)
t
CKmin
(IDD)
t
CKmin
(IDD)
t
RC
n.a.
n.a.
n.a.
n.a.
t
RAS
n.a.
n.a.
n.a.
n.a.
t
RCD
n.a.
n.a.
n.a.
n.a.
t
RRD
n.a.
n.a.
n.a.
n.a.
CL
n.a.
n.a.
n.a.
n.a.
AL
n.a.
n.a.
n.a.
n.a.
CS
HIGH
STABLE
HIGH
STABLE
Bank Address, Row Addr. and
Command Inputs
SWITCHING as
described in Table 2
STABLE
STABLE
STABLE
Data inputs
SWITCHING
FLOATING
FLOATING
FLOATING
Output Buffer DQ,DQS / MR1 bit A12
off / 1
off / 1
off / 1
off / 1
Rtt_NOM, Rtt_WE
disabled
disabled
disabled
disabled
Burst length
n.a.
n.a.
n.a.
n.a.
Active banks
none
none
none
none
Idle banks
all
all
all
all
Precharge Power
Down Mode / Mode Register Bit
a
n.a.
Fast Exit / 1
(any valid command after
tXP
1
)
Slow Exit / 0
Slow exit (RD and ODT
commands must satisfy
tXPDLL-AL)
n.a.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK
0
IDD2N /IDD3N Measurement Loop
BA[2:0]
ADDR[13:0]
CS
RAS
CAS
WE
CMD
DQ[7:0]
DM
7
0
0000
3FFF
0000
D
D
D
D
Figure 21. IDD2N /IDD3N Example (DDR3-800-666, 1Gb X8)
D
D
D
D
D
D
D
FF
00
00
FF FF
00
00
FF FF
00
00
FF FF
00
00
FF FF
00
00
FF FF
00
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