參數(shù)資料
型號(hào)： K4B1G0446C-CF8
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 1Gb C-die DDR3 SDRAM Specification
中文描述： 1Gb的?芯片的DDR3 SDRAM規(guī)范
文件頁(yè)數(shù)： 37/63頁(yè)
文件大?。?/td> 1255K
代理商： K4B1G0446C-CF8
Page 37 of 63
Rev. 1.0 June 2007
1Gb DDR3 SDRAM
K4B1G04(08/16)46C
[ Table 37 ] IDD Measurement Conditions for IDD4R, IDD4W and IDD7
Current
IDD4R
IDD4W
IDD7
Name
Operating Current Burst Read
Operating Current Burst Write
All Bank Interleave Read Current
Measurement Condition
Timing Diagram Example
Figure 3
CKE
HIGH
HIGH
HIGH
External Clock
on
on
on
t
CK
t
CKmin
(IDD)
t
CKmin
(IDD)
t
CKmin
(IDD)
t
RC
n.a.
n.a.
t
RCmin
(IDD)
t
RAS
n.a.
t
RASmin
(IDD)
t
RCD
n.a.
n.a.
t
RCDmin
(IDD)
t
RRD
n.a.
n.a.
t
RRDmin
(IDD)
CL
CL(IDD)
CL(IDD)
CL(IDD)
AL
0
0
t
RCDmin
-1t
CK
CS
HIGH btw. valid cmds
HIGH btw. valid cmds
HIGH btw. valid cmds
Command Inputs
(CS, RAS, CAS, WE)
SWITCHING as described in Table 2;
exceptions are Read commands =>
IDD4R Pattern:
R0DDDR1DDDR3DDDR3DDDR4 .....
Rx = Read from bank x;
Definition of D and D: see Table 2
SWITCHING as described in Table 2;
exceptions are Write commands =>
IDD4W Pattern:
W0DDDW1DDDW2DDDW3DDD W4 ...
Wx = Write to bank x;
Definition of D and D: see Table 2
For patterns see Table 9
Row, Column Addresses
column addresses
SWITCHING as described in Table 2;
Address Input A10 must be LOW all the
time!
column addresses
SWITCHING as described in Table 2;
Address Input A10 must be LOW all the
time!
STABLE during
DESELECTs
Bank Addresses
bank address cycling (0 ->1 -> 2 -> 3 ...)
bank address cycling (0 ->1 -> 2 -> 3 ...)
bank address cycling (0 ->1 -> 2 -> 3 ...),
see pattern in Table 9
DQ I/O
Seamless Read Data Burst (BL8): output
data switches every clock, which means
that Read data is stable
during one clock cycle.
To achieve Iout = 0mA the output buffer
should be switched off by MR1 Bit A12 set
to "1".
Seamless Write Data Burst (BL8): input
data switches every clock, which means
that Write data is stable during one clock
cycle.
DM is low all the time.
Read Data (BL8): output data switches
every clock, which means that Read
data is stable during one clock cycle.
To achieve Iout = 0mA the output buffer
should be switched off by MR1 Bit
A12 set to "1".
Output Buffer DQ,DQS / MR1 bit A12
off / 1
off / 1
off / 1
Rtt_NOM, Rtt_WE
disabled
disabled
disabled
Burst length
8 fixed / MR0 Bits [A1, A0] = {0,0}
8 fixed / MR0 Bits [A1, A0] = {0,0}
8 fixed / MR0 Bits [A1, A0] = {0,0}
Active banks
all
all
all
Idle banks
none
none
none
Precharge Power Down Mode
/ Mode Register Bit
n.a.
n.a.
n.a.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4B1G0446C-ZCF7 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb C-die DDR3 SDRAM Specification
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K4B1G0446D 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb D-die DDR3 SDRAM Specification
K4B1G0446D-HCF7 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb D-die DDR3 SDRAM Specification
K4B1G0446D-HCF8 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb D-die DDR3 SDRAM Specification
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